PLL Synchronization Using Common Triggers for Phase-Coherent MIMO
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Solution Overview
Problem
Existing wireless communication systems face challenges in achieving phase coherence between multiple oscillator signals, particularly in coherent uplink multiple-input and multiple-output (MIMO) communications, due to limitations in synchronizing phase-locked loop (PLL) circuits, which affect signal quality and compliance with 5G NR wireless standards.
Innovation Solution
The method and apparatus synchronize PLL circuits by triggering them to perform actions such as initialization, frequency hopping, and frequency correction simultaneously within allowable phase errors, using a common trigger mechanism to ensure phase coherence, thereby enhancing synchronization of PLL-based voltage-controlled oscillators and reference clock dividers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple PLL circuits operate independently, then each circuit can function autonomously, but phase coherence between oscillator signals deteriorates
Solution Approach 1:
The patent merges the synchronization control of multiple PLL circuits by introducing a common trigger mechanism that simultaneously initiates synchronization actions across all PLL circuits. This combining approach ensures phase coherence is maintained without requiring complex inter-circuit communication or feedback systems.
Solution Approach 2:
The patent applies preliminary action by pre-synchronizing the PLL circuits before coherent uplink MIMO transmission begins. The common trigger initiates synchronization actions in advance, ensuring that all oscillator signals are phase-aligned before the communication protocol starts, thereby eliminating the need for continuous complex synchronization during operation.
2Reliability
If PLL circuits are synchronized with common trigger, then phase coherence improves, but system complexity increases
Solution Approach 1:
The patent segments the synchronization function by implementing separate, identical synchronization circuits in each transmit path, all controlled by the same common trigger. This segmentation allows each PLL to be synchronized independently yet simultaneously, maintaining signal quality while avoiding the need for complex centralized control mechanisms.
3Reliability
If synchronization actions are performed simultaneously, then phase coherence is maintained, but timing precision requirements increase
Solution Approach 1:
The patent enables each PLL circuit to perform its own synchronization actions autonomously in response to the common trigger. Each PLL's internal mechanisms handle the actual phase adjustment and locking processes independently, reducing the timing precision requirements for the external trigger signal while maintaining overall phase coherence.
Data Source
AI summary
Aspects of the present disclosure provide techniques and apparatus for synchronizing phase-locked loop (PLL) circuits. An example method of operating PLL circuits includes obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit; and performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication.