PLL TDC Gain Calibration Using DCO Period Feedback Pulses
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Solution Overview
Problem
Conventional PLLs face challenges in accurately determining gain relationship during normal operation, particularly in fractional-N PLLs, often requiring the PLL to be taken out of lock for calibration, which disrupts the clock signal synchronization.
Innovation Solution
A method and apparatus that utilize a time-to-digital converter (TDC) to simultaneously provide phase error and gain information during normal PLL operation, enabling continuous calibration without disrupting lock, by using a feedback clock pulse width equal to the DCO output period for enhanced phase and gain detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PLL calibration methods are used to determine gain relationship, then calibration can be performed, but the PLL must be taken out of lock which disrupts clock signal synchronization
Solution Approach 1:
The patent enables continuous calibration by maintaining the PLL in lock state throughout the gain relationship determination process. The TDC continuously measures phase differences between reference and feedback clock signals, allowing calibration to proceed without interrupting the clock signal synchronization that the PLL provides.
Solution Approach 2:
The patent introduces a TDC as an intermediary device that measures phase differences between clock signals. By using the TDC output and incorporating a gain adjustment mechanism, the system can determine the gain relationship indirectly through phase error measurements rather than requiring direct manipulation of the PLL lock state.
2Measurement precision
If algorithmic gain adjustment is used to minimize error, then gain relationship can be determined, but the process is complex and requires taking PLL out of lock
Solution Approach 1:
The patent implements a self-calibrating mechanism where the TDC continuously provides phase error information that automatically reflects the gain relationship. The system uses the natural phase differences measured during normal operation to determine calibration parameters without requiring external intervention or complex algorithmic processing.
Solution Approach 2:
The patent employs feedback from the TDC phase error measurements to continuously monitor and determine the gain relationship. By feeding back the TDC output information through a gain adjustment mechanism, the system can determine calibration parameters using straightforward phase error analysis rather than complex algorithms.
Data Source
AI summary
A phase-locked loop (PLL) includes a digitally controlled oscillator (DCO) that generates a DCO output signal. A feedback divider is coupled to the DCO output signal, divides the DCO output signal, and generates a feedback clock signal. The feedback clock signal is generated as a pulse having a pulse width equal to one period of the DCO output signal. A time-to-digital converter (TDC) receives a reference clock signal and the feedback clock signal and generates a TDC output that indicates a phase difference between the reference clock signal and the feedback clock signal. The TDC output also provides gain information indicating how many delay elements correspond to the period of the DCO output signal. The gain information can be used to more accurately cancel quantization error in the PLL.