PLL Test Circuit with TDC for Single-Pattern SHMOO Verification
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Solution Overview
Problem
Existing methods for verifying the function of a device under test (DUT) in a phase locked loop (PLL) require multiple test patterns to adjust output frequency and duty cycle, leading to inefficiencies in time and resource allocation.
Innovation Solution
A circuit architecture incorporating a digital converter, evaluation circuit, and duty correction circuit that allows for a single test pattern to adjust both frequency and duty cycle, using a lookup table to determine parameter levels and integrate a time-to-digital converter (TDC) to streamline the SHMOO test process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple test patterns are used to adjust output frequency and duty cycle, then verification accuracy is improved, but test time and resource allocation deteriorate
Solution Approach 1:
The patent combines multiple test patterns into a single integrated test pattern that simultaneously controls both output frequency and duty cycle. The circuit architecture integrates a frequency control unit and a duty cycle control unit that work together with one test pattern, eliminating the need for separate test patterns for each parameter adjustment.
Solution Approach 2:
The test pattern is designed to serve multiple functions simultaneously: it controls both the output frequency and duty cycle of the PLL, and it verifies multiple functions of the DUT across different operating conditions. This multi-functional test pattern replaces what previously required multiple separate test patterns.
2Adaptability or versatility
If multiple test patterns are used to adjust output frequency and duty cycle, then parameter coverage is improved, but resource allocation deteriorates
Solution Approach 1:
The patent merges the resource requirements of multiple test patterns into a single unified test pattern structure. The circuit architecture combines the control resources for frequency and duty cycle into shared components, reducing overall resource allocation while maintaining comprehensive parameter coverage.
Solution Approach 2:
The single test pattern is designed with universal control capabilities that cover multiple parameters (frequency and duty cycle) and verify multiple DUT functions. This multi-functional approach eliminates the need for separate dedicated resources for each parameter test, optimizing resource allocation.
3Productivity
If a single test pattern is used to adjust frequency and duty cycle, then time efficiency is improved, but control precision may deteriorate
Solution Approach 1:
The single test pattern is segmented into distinct control fields: a frequency control field and a duty cycle control field. Each field independently controls its respective parameter with full precision, allowing the single test pattern to maintain the control precision of multiple separate patterns while improving time efficiency.
Solution Approach 2:
The test pattern incorporates independent parameter control mechanisms that allow simultaneous adjustment of frequency and duty cycle without interfering with each other's precision. The circuit architecture uses separate control paths for each parameter that converge in the single test pattern, maintaining full control precision for both parameters.
Data Source
AI summary
A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.