Digital PLL Integrator With Window Comparator for Compact Phase Lock
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Solution Overview
Problem
Conventional phase-locked loop systems face challenges in achieving phase lock due to high or low reference frequencies, requiring large external capacitors and high power consumption, making integration in modern IC technologies difficult.
Innovation Solution
A phase-locked loop circuit that digitizes the output of a digital phase detector using a sigma-delta modulator as a decimator and down-sampler, eliminating the need for external components and reducing power dissipation, featuring a digital window comparator for temperature compensation and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an integrator with a compensating zero is implemented using a charge pump circuit and series resistor-capacitor, then the loop filter can attenuate high-frequency portions of the correction signal, but the required capacitance is very large (much greater than 1 nF) making it difficult to integrate into IC technologies
Solution Approach 1:
The patent replaces the conventional analog charge pump circuit with a digital domain implementation. The digital integrator uses digital logic circuits (D-flip flops, XOR gates, AND gates) to perform the integration function that was previously achieved through analog RC circuits, thereby eliminating the need for large external capacitors and enabling IC integration.
Solution Approach 2:
The patent changes the operating domain from analog to digital. By digitizing the phase detector output and performing integration in the digital domain, the system transforms continuous voltage signals into discrete digital values, allowing the use of digital logic instead of analog components with large capacitance values.
2Reliability
If conventional analog phase-locked loop components are used, then the system can achieve phase lock, but the power consumption is high and the board space requirements are large
Solution Approach 1:
The patent substitutes analog components with digital equivalents throughout the phase-locked loop system. The digital phase detector, digital integrator, and digital control logic replace analog circuits, resulting in lower power consumption while maintaining phase lock functionality. Digital circuits operate at lower voltages and consume less power compared to their analog counterparts.
Solution Approach 2:
The digital integrator circuit performs multiple functions: it integrates the phase error signal, provides temperature compensation through the digital window comparator, and generates the control signal for the voltage-controlled oscillator. This multi-functionality reduces the overall component count and power consumption compared to separate analog circuits for each function.
3Reliability
If conventional analog phase-locked loop components are used, then the system can achieve phase lock, but the board space requirements are large making integration in modern IC technologies difficult
Solution Approach 1:
The patent replaces analog components that require large physical space (resistors, capacitors, operational amplifiers) with digital logic circuits that can be densely integrated on a chip. The digital integrator using D-flip flops and logic gates occupies significantly less area than the equivalent analog RC integrator with large capacitors.
Solution Approach 2:
The patent implements a compact digital integrator structure where multiple functions are nested within a single circuit block. The D-flip flops, XOR gates, and AND gates are arranged in a nested configuration where the output of one stage feeds into the next, maximizing space utilization and minimizing the overall circuit footprint.
Data Source
AI summary
In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.