PLL Frequency Synthesizer Zero-Cross Timing for Low Spurious Noise
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Solution Overview
Problem
Existing frequency synthesizers face limitations in achieving low noise and simplified circuit configurations due to A/D and D/A conversion, which affects spurious characteristics and phase noise, especially when generating reference signals for communication devices.
Innovation Solution
A signal generating device that outputs a pulse signal based on the timing of a sawtooth wave crossing a threshold value, using a clock source, integrated waveform generation, clock information output, coefficient calculation, and clock selection to determine the use ratio between clock signals, thereby improving spurious characteristics without requiring A/D and D/A conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If A/D conversion and D/A conversion are performed to generate frequency signals, then the frequency can be controlled precisely, but the circuit complexity increases and spurious characteristics deteriorate
Solution Approach 1:
The patent extracts and eliminates the A/D conversion stage from the frequency synthesis system. By using a digital signal to directly control the timing of clock signals through logical operations, the system achieves precise frequency control without requiring analog-to-digital conversion, thereby simplifying the circuit while maintaining control precision.
Solution Approach 2:
The patent replaces the analog D/A conversion mechanism with a digital logic system. Instead of converting digital signals back to analog voltages to control oscillators, the invention uses digital clock signal timing and logical operations (AND, OR, NOT gates) to directly generate the frequency output, substituting analog conversion with digital signal processing.
2Measurement precision
If A/D conversion and D/A conversion are performed to generate frequency signals, then the frequency can be controlled precisely, but the spurious characteristics worsen
Solution Approach 1:
The patent removes the A/D conversion stage which is a major source of spurious signals. By using purely digital signal processing to control clock timing, the system eliminates the analog conversion processes that generate spurious emissions, while still achieving precise frequency control through digital timing operations.
Solution Approach 2:
The patent converts the potential harm of digital quantization effects into a benefit by using them to generate precise clock timing signals. The digital nature of the signals, which could introduce quantization noise, is instead utilized to create clean, precisely timed clock edges that drive the frequency synthesis, turning a potential source of spurious signals into a source of precision.
3Measurement precision
If linear interpolation is performed on analog triangular wave to fix zero cross timing, then the frequency accuracy improves, but the phase noise increases when used in PLL
Solution Approach 1:
The patent replaces the analog triangular wave generation and interpolation system with a digital clock signal timing system. Instead of generating analog waves and detecting zero crossings, the invention uses digital logic to directly generate precisely timed clock signals, eliminating the phase noise introduced by analog interpolation while maintaining timing accuracy.
Solution Approach 2:
The patent extracts and eliminates the analog triangular wave generation and zero-cross detection mechanism. By using digital clock signals with predetermined timing, the system removes the interpolation process that introduces phase noise, achieving accurate timing detection through digital logic operations instead.
Data Source
AI summary
A frequency synthesizer using a PLL has a simple structure and excellent spurious characteristics. A reference frequency signal inputted into a phase comparison unit is generated based on a clock when a zero cross point of a sawtooth wave composed of a digital signal is detected. However, in this case, since the digital values are skipped values, the digital value does not always become zero when its positive/negative sign is inverted. Hence, where the clock signals reading the digital value immediately before and the digital value immediately after the zero cross time when the positive/negative sign is inverted in a region where the digital value gradually changes are P1 and P2 respectively and the clock signal at a timing next to the clock signal P2 is P3, P1 and P3 are used at a ratio corresponding to the ratio between the digital values read by P1 and P2.