Plural-Register Load Instruction Processing with Atomicity Tracking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Data processing systems face inefficiencies when handling plural-register-load instructions due to insufficient bandwidth, leading to potential loss of atomicity and reduced performance, as existing approaches either require reserved load pipelines or delay processing, limiting the utilization of available bandwidth.

Innovation Solution

The system issues load operations corresponding to plural-register-load instructions as separate operations, allowing them to span multiple cycles, and employs load tracking circuitry to detect and address loss-of-atomicity conditions, ensuring atomicity while optimizing bandwidth usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If load operations are issued as separate operations to utilize available bandwidth, then bandwidth utilization is improved, but atomicity cannot be guaranteed

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidatomicity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the plural-register-load instruction into multiple separate load operations that can be issued independently to different pipelines. This segmentation allows each load operation to be processed separately, maximizing bandwidth utilization while the load tracking circuitry ensures atomicity is maintained by detecting and handling re-ordering scenarios.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The load tracking circuitry implements a feedback mechanism that monitors the execution status of each load operation and detects re-ordering conditions. When a loss-of-atomicity condition is detected, the system requests re-processing of the affected instruction, providing feedback control that ensures atomicity is maintained despite separate operation issuance.

Inventive Principle:
Principle #23Feedback

2Reliability

If load operations are delayed to maintain atomicity, then atomicity is preserved, but processing speed and bandwidth utilization are reduced

Engineering Contradiction:
ImproveatomicityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system performs preliminary actions by issuing all load operations immediately without waiting for atomicity verification. The load tracking circuitry then monitors execution in the background, and only requests re-processing if atomicity is compromised. This preliminary issuance approach maximizes processing speed while maintaining atomicity through post-hoc verification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The load tracking circuitry operates autonomously to monitor and detect atomicity violations without blocking the main execution flow. The system serves itself by automatically detecting loss-of-atomicity conditions and requesting re-processing only when necessary, eliminating the need for conservative delays while preserving atomicity.

Inventive Principle:
Principle #25Self-service

3Reliability

If load pipelines are reserved for plural-register-load instructions, then atomicity is maintained, but bandwidth utilization and pipeline efficiency are reduced

Engineering Contradiction:
ImproveatomicityVSAvoidpipeline efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent makes load pipelines universal by allowing them to handle both singular and plural register load operations. Instead of reserving specific pipelines for plural-register-load instructions, any available pipeline can execute any load operation. The load tracking circuitry ensures atomicity is maintained regardless of which pipelines are used, enabling full utilization of all pipelines for all types of load instructions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11314509B2Processing of plural-register-load instruction
Publication Date: 2022.04.26 ARM LTD
  • US11314509B2 patent drawing
  • US11314509B2 patent drawing
  • US11314509B2 patent drawing

AI summary

An apparatus comprises processing circuitry to issue load operations to load data from memory. In response to a plural-register-load instruction specifying at least two destination registers to be loaded with data from respective target addresses, the processing circuitry permits issuing of separate load operations corresponding to the plural-register-load instruction. Load tracking circuitry maintains tracking information for one or more issued load operations. When the plural-register-load instruction is subject to an atomicity requirement and the plurality of load operations are issued separately, the load tracking circuitry detects, based on the tracking information, whether a loss-of-atomicity condition has occurred for the load operations corresponding to the plural-register-load instruction, and requests re-processing of the plural-register-load instruction when the loss-of-atomicity condition is detected.