Concurrent Instruction Execution TRIZ Cases
- Array Processor Macro-Instruction Zero-Latency Data Movement
Processor uses macro-instructions for zero-latency data movement, reducing intermediate memory overhead during complex N-dimensional array processing.
- Storage Checkpointing in Mirrored Virtual Machine Systems
A storage controller saves modifying operation data to a checkpointing region while preserving previous states for non-destructive updates.
- UTM Transaction Suspension via OS Ring Transitions
Saving transaction state in a register during kernel mode ring transitions prevents automatic aborts when handling hardware exceptions.
- Reduced Size Register View Data Structure for Microprocessor Context Switching
Register view snapshots track machine state via templates, eliminating full hardware duplication to reduce context switch time and area.
- Hazard Prediction Buffer for Memory Access Groups
A hazard prediction buffer stores entries for groups of memory access instructions to enable accurate out-of-order execution.
- Speculative Buffer with Context Tagging for Cache Side-Channel Isolation
Separate speculative buffers tagged with execution context identifiers isolate data from the main cache, preventing timing side-channel attacks.
- Prefetch Strategy Control for Parallel Thread Execution
Prefetch strategy selection circuitry detects program instruction characteristics to dynamically choose between short-running and long-running prefetch modes.
- Plural-Register Load Instruction Processing with Atomicity Tracking
Load tracking circuitry detects loss-of-atomicity conditions when issuing separate load operations, requesting re-processing to maintain data integrity.
- Processor Error Recovery via State Snapshot and Dynamic Precision Switching
A processor restores a pre-computation state snapshot when an error indicator detects accumulated approximation errors exceeding a defined bound.
- Event Counting Branch Prediction Circuitry Checkpoint Storage Reduction
Event counting prediction circuitry separates training and active storage to reduce checkpoint state requirements in out-of-order processors.
- Augmented Event Code Verification for Data Processing Accuracy
System assigns code-wise risk scores to augmented event codes, resolving inaccurate determinations from unverified external sources.
- Data Service-Aware IO Scheduler Request Alignment
A data service-aware input output scheduler aligns storage requests with configured segment sizes to optimize throughput and reduce latency.
- Delayed Lock Step Processor Fault Recovery
Delayed lock step execution detects faults via comparators before writeback, reducing recovery cycle loss to under ten cycles.
- Hardware Prefetcher Suppression via Control Logic
Selective hardware prefetch suppression resolves pipeline throughput bottlenecks caused by speculative cache misses and latency.
- Tensor Prefetching for Deep Learning Memory Latency
Processor prefetches tensors using stored allocation patterns to reduce memory access latency during deep learning training iterations.