Transactional Register Save Mask for Atomic Multiprocessor Updates

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Solution Overview

Problem

In multiprocessor programming, updating multiple storage locations simultaneously by multiple CPUs is challenging due to the need for serialization, which often results in coarse-grained locking, leading to potential deadlocks and recovery issues, and existing solutions do not efficiently handle exception conditions in transactional processing.

Innovation Solution

A transactional execution facility is introduced, allowing CPUs to perform transactions that access multiple storage locations atomically, with features like nested transactions, constrained and nonconstrained execution modes, and specialized instructions for managing transactions and diagnostics, enabling finer-grained serialization and improved exception handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If lock words are used for interlocked update of multiple storage locations, then atomicity of updates is improved, but serialization granularity becomes too coarse leading to deadlocks and reduced productivity

Engineering Contradiction:
Improveatomicity of updatesVSAvoidserialization overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the update operation into two distinct phases: a read phase where multiple storage locations are fetched without serialization, and a write phase where updates are performed atomically using test-and-set instructions. This segmentation allows concurrent reads while ensuring atomic writes, thereby maintaining reliability while improving productivity by reducing unnecessary serialization overhead.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary fetching of multiple storage locations into processor registers before the actual update operation. By pre-loading the data that needs to be updated, the system avoids the need for serialized access during the read phase, allowing multiple CPUs to concurrently access these locations without deadlocks, while still ensuring atomic updates when the write phase executes.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If fine-grained serialization is implemented through hierarchical lock points, then productivity is improved, but system complexity and deadlock risk increase

Engineering Contradiction:
Improveserialization efficiencyVSAvoidlock hierarchy management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the serialization requirement from the read operation and concentrates it only in the write operation. By using test-and-set instructions exclusively for the update phase while allowing free reading in the fetch phase, the system achieves fine-grained serialization efficiency without the complexity of hierarchical lock management. This extraction eliminates the need for multiple lock points and their associated deadlock risks.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If recovery environment is established for exception handling, then reliability is improved, but processing overhead and complexity increase

Engineering Contradiction:
Improveexception handling capabilityVSAvoidrecovery environment setup
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service exception handling through processor flags and automatic rollback mechanisms. When an exception occurs during transactional processing, the processor automatically detects the error condition via status flags and rolls back the transaction without requiring external recovery environments. This self-service approach maintains reliability by ensuring proper exception handling while reducing the complexity associated with establishing separate recovery infrastructure.

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP2862092B1Saving/restoring selected registers in transactional processing
Publication Date: 2019.03.13 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • EP2862092B1 patent drawingFigure 1
  • EP2862092B1 patent drawingFigure 2A~3B
  • EP2862092B1 patent drawingFigure 4~5

AI summary

A transaction begin instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.