UTM Transaction Suspension via OS Ring Transitions
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Solution Overview
Problem
Unbounded transactional memory (UTM) systems face challenges in handling user-level asynchronous events, such as hardware exceptions, which can lead to incorrect operations and performance slowdowns due to automatic transaction aborts and restarts, especially when frequent exception handling occurs.
Innovation Solution
A combination of hardware support in processors, UTM runtime system code, and operating system code enables improved handling of exceptions and interrupts during UTM transactions, allowing transactions to be suspended and resumed without automatic abort, using mechanisms like read-write transaction control registers and software-defined events to manage asynchronous and synchronous events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If hardware exceptions are handled by OS user runtime code during UTM execution, then exception handling capability is improved, but transaction correctness deteriorates due to asynchronous intervention
Solution Approach 1:
The patent introduces an intermediary mechanism (transaction suspension and resumption interface) between the OS exception handling code and the UTM transaction execution. When an exception occurs, the transaction is temporarily suspended and can be resumed after exception handling, allowing both OS exception handling and UTM transaction correctness to coexist without direct conflict
2Reliability
If UTM transactions are aborted upon hardware exception, then transaction integrity is improved, but performance deteriorates due to frequent aborts and restarts
Solution Approach 1:
The patent implements a dynamic transaction handling approach where the transaction state can transition between executing, suspended, and resumed states. Instead of statically aborting transactions on exception, the system dynamically suspends them during exception handling and resumes them afterward, maintaining integrity while avoiding unnecessary aborts and performance degradation
3Speed
If UTM hardware acceleration is used, then execution speed is improved, but compatibility deteriorates due to requirements for specially compiled code
Solution Approach 1:
The patent segments the code execution into two distinct parts: UTM-compiled code that runs with hardware acceleration for performance-critical transactional sections, and default OS runtime code that handles exceptions and non-transactional operations. This segmentation allows the system to maintain both high performance through hardware acceleration and broad compatibility through standard OS runtime support
Data Source
AI summary
In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.