Processor Operations Scheduler with Tracking Array and Counter

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Solution Overview

Problem

Conventional processors face inefficiencies due to dependent operations being repeatedly blocked by schedulers, leading to prolonged pending times and reduced processing efficiency.

Innovation Solution

A processing system that tracks pending operations and prioritizes scheduling when a threshold number of blocked operations is exceeded, using a tracking array and counter to ensure dependent operations are not indefinitely delayed, by prioritizing operations stored in the tracking array for execution once the counter value surpasses a threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional schedulers block dependent operations to prevent execution errors, then reliability is improved, but processing efficiency deteriorates due to prolonged pending times

Engineering Contradiction:
Improveexecution correctnessVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The scheduler dynamically adjusts its behavior based on the pending operation count. When dependent operations are blocked, the scheduler monitors the queue and dynamically switches between strict dependency enforcement and prioritizing ready operations, resolving the contradiction between reliability and productivity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the scheduling parameter (priority assignment) based on the state of the operation queue. When the number of pending operations exceeds a threshold, the scheduler changes priority assignments to favor ready operations over blocked dependent operations, balancing reliability and efficiency

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the scheduler strictly enforces operation dependencies, then execution correctness is improved, but processing delays increase due to repeated blocking

Engineering Contradiction:
Improvedependency correctnessVSAvoidpending time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The scheduler applies partial dependency enforcement by allowing ready operations to proceed even when some dependent operations are blocked. This partial action approach prevents complete blocking while still maintaining correctness for operations that are ready to execute

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The scheduler implements feedback monitoring of the pending operation queue. When the queue depth exceeds a threshold, the scheduler receives feedback and adjusts its scheduling decisions to reduce blocking, thereby reducing pending time while maintaining dependency correctness

Inventive Principle:
Principle #23Feedback

3Productivity

If the scheduler allows out-of-order execution to improve efficiency, then processing speed is improved, but execution errors may occur due to violated dependencies

Engineering Contradiction:
Improveprocessing speedVSAvoidexecution correctness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The scheduler dynamically determines execution order based on real-time conditions. When dependencies are satisfied, operations execute out-of-order for speed; when dependencies are violated, the scheduler dynamically adjusts to maintain correctness, resolving the speed-correctness tradeoff

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different operations receive different scheduling treatments based on their local dependency status. Ready operations are scheduled immediately for speed, while dependent operations are handled differently, creating local quality variations in scheduling policy that balance speed and correctness

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3488339B1Scheduling independent and dependent operations for processing
Publication Date: 2022.04.20 ADVANCED MICRO DEVICES INC
  • EP3488339B1 patent drawingFigure 1
  • EP3488339B1 patent drawingFigure 2
  • EP3488339B1 patent drawingFigure 3

AI summary

A processor (100) includes an operations scheduler (105) to schedule execution of operations at, for example, a set of execution units (110) or a cache of the processor. The operations scheduler periodically adds sets of operations to a tracking array (120), and further identifies when an operation in the tracked set is blocked from execution scheduling in response to, for example, identifying that the operation is dependent on another operation that has not completed execution. The processor further includes a counter (130) that is adjusted each time an operation in the tracking array is blocked from execution, and is reset each time an operation in the tracking array is executed. When the value of the counter exceeds a threshold (135), the operations scheduler prioritizes the remaining tracked operations for execution scheduling.