3D Substrate Routing for PMIC Inductor Placement
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Solution Overview
Problem
Conventional power management integrated circuits (PMICs) face inefficiencies in substrate routing due to the need to place inductors near the PMIC for lower direct current resistance, leading to wasted space and increased resistance when inductors are placed in corner regions.
Innovation Solution
A system that includes a substrate with a first device attached near the center and a second device attached near the edge, connected by a conductive link on the substrate surface, utilizing 3D space to reduce resistance and create a shorter inductive path, while allowing for increased component density and protection from oxidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inductors are placed near the PMIC device, then direct current resistance is reduced, but substrate floor plan area is wasted
Solution Approach 1:
The patent transitions from conventional 2D planar routing to 3D vertical routing by extending conductive vias through multiple substrate layers. This allows inductors to be placed in corner regions while maintaining low DCR through vertical conductive paths, effectively utilizing the third dimension to resolve the space-resistance tradeoff.
Solution Approach 2:
The patent embeds conductive vias within the substrate structure, nesting multiple conductive layers vertically. This nested arrangement creates compact 3D routing paths that connect inductors in corner regions to the PMIC with minimal resistance while maximizing substrate space utilization.
2Area of stationary object
If inductors are placed in corner regions, then space utilization is improved, but direct current resistance increases
Solution Approach 1:
The patent employs vertical 3D routing through multi-layer conductive vias to connect corner-placed inductors to the PMIC. This vertical dimension provides direct conductive paths that minimize horizontal traversal distance, thereby maintaining low DCR while enabling compact corner placement of inductors.
Solution Approach 2:
The patent creates localized high-density conductive regions at via locations with multiple stacked conductive layers. This local concentration of conductive material reduces resistance at critical connection points between corner inductors and the PMIC, compensating for the increased path length.
Data Source
AI summary
Terminal connection routing on top of a substrate surface connects to component terminals to and from PMIC devices and provides a novel structure to connect surface mount technology (SMT) passive device terminals on an SMT layer (such as a Cu bar mesh) that uses the 3D space available near to components to lower resistance/lower inductive path and provides a shorter path, SIP form factor reduction, a component placement density increase, creates an additional PDN layer for connectivity and, if the routing is encapsulated in a mold, protects the metal in the connection from oxidation. Methods are presented for providing a substrate, attaching a first device to a first surface of the substrate near a center of the substrate, attaching a second device to the first surface of the substrate near an edge of the substrate, and connecting a connection located on the first surface of the substrate between the first device and the second device.