PMIC Phase-Shifted Converter Clocks for EMI Reduction

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Solution Overview

Problem

Existing power management integrated circuits (PMICs) suffer from issues such as switching noise, increased capacitance of input filter capacitors, and electromagnetic interference (EMI), particularly due to the use of multiple switching converters operating at constant frequencies, which can lead to errors and require precise phase adjustment considering environmental factors.

Innovation Solution

A power management integrated circuit (PMIC) that includes a clock generator and multiple phase delay controllers to generate supply clocks with different phases for each switching converter, using digital logic circuits and phase delay controllers to adjust these phases accurately, thereby reducing EMI and improving precision.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple switching converters operate at constant frequency, then power conversion is efficient, but electromagnetic interference and switching noise increase

Engineering Contradiction:
Improvepower conversion efficiencyVSAvoidelectromagnetic interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent implements dynamic phase adjustment by introducing a phase delay controller that varies the operating phases of multiple switching converters based on temperature, process, and voltage conditions. This dynamic adaptation allows the system to maintain efficient power conversion while reducing electromagnetic interference by optimizing phase relationships in real-time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the phase parameter of switching converters dynamically. By adjusting phase delay according to environmental factors (temperature, process, voltage), the system maintains optimal operating conditions that balance conversion efficiency with reduced electromagnetic interference, rather than using fixed constant frequency operation.

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If phase delay is adjusted to reduce EMI, then electromagnetic interference decreases, but accuracy of phase adjustment becomes more difficult due to environmental factors

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidphase adjustment accuracy
Core Design Contradiction:
Object-generated harmful factorsVSMeasurement precision

Solution Approach 1:

The patent implements feedback mechanisms through phase delay controllers that monitor environmental conditions (temperature, process, voltage) and adjust phase relationships accordingly. This closed-loop approach compensates for environmental variations, maintaining accurate phase adjustment while minimizing electromagnetic interference across different operating conditions.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adapts phase delay settings based on real-time environmental monitoring. By making phase adjustment dynamic rather than static, the system maintains precision across varying temperature, process, and voltage conditions while effectively reducing electromagnetic interference.

Inventive Principle:
Principle #15Dynamics

3Object-generated harmful factors

If separate phase delay controllers are used for each switching converter, then EMI is reduced, but device complexity increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidnumber of phase delay controllers
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent combines multiple phase delay control functions into integrated control architecture. Rather than completely separate controllers for each converter, the system uses coordinated phase delay controllers that can manage multiple converters, reducing overall device complexity while maintaining the EMI reduction benefits of individual phase control.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250279771A1Power management integrated circuit
Publication Date: 2025.09.04 SAMSUNG ELECTRONICS CO LTD
  • US20250279771A1 patent drawing
  • US20250279771A1 patent drawing
  • US20250279771A1 patent drawing

AI summary

A power management integrated circuit including: a clock generator that generates an input clock; a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter; a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter; and a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter, wherein the first phase, the second phase and the third phase have different phases from each other.