PMIC Clock Phase Control for Multi-Converter EMI Reduction
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Solution Overview
Problem
Existing power management integrated circuits (PMICs) face challenges with electromagnetic interference (EMI) due to the operation of multiple switching converters, leading to errors and inefficiencies in power management, especially as the number of converters and environmental factors like temperature, process, and voltage variations increase.
Innovation Solution
The proposed power management integrated circuit incorporates a clock generator and multiple phase delay controllers that generate supply clocks with different phases for each switching converter, allowing for precise phase adjustment to mitigate EMI and improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple switching converters operate with constant frequency clocks, then power conversion is achieved, but electromagnetic interference (EMI) increases causing errors and reduced reliability
Solution Approach 1:
The patent applies periodic action by introducing phase delay control to multiple switching converters. Each converter operates with a clock signal that has a different phase delay, creating periodic switching patterns that are staggered in time. This periodic staggering reduces the cumulative electromagnetic interference while maintaining the power conversion function of each converter.
Solution Approach 2:
The patent changes the phase parameter of clock signals supplied to different switching converters. By adjusting the phase delay of each converter's operating clock independently, the system modifies the timing parameters of switching operations to minimize EMI while maintaining conversion efficiency and reliability.
2Object-generated harmful factors
If phase delay controllers are added to adjust operating clocks, then EMI is reduced, but device complexity increases due to additional components and environmental factor variations
Solution Approach 1:
The patent merges the phase delay control functionality into the existing clock distribution architecture of the PMIC. Rather than adding completely separate control systems, the phase delay controllers are integrated with the clock generator and distribution network, sharing common components and control logic to reduce overall system complexity.
Solution Approach 2:
The phase delay controllers are designed with multi-functionality, serving both EMI reduction and clock synchronization purposes. The same control mechanism that adjusts phase delays for EMI mitigation also ensures proper timing coordination among multiple converters, eliminating the need for separate synchronization circuits.
3Productivity
If the number of switching converters is increased to meet power management demands, then power conversion capability is improved, but EMI and measurement precision deteriorate
Solution Approach 1:
The patent implements feedback mechanisms in the phase delay controllers to maintain precise phase adjustment accuracy. By monitoring the actual phase delays and comparing them with target values, the system automatically corrects deviations caused by environmental factors such as temperature and voltage variations, ensuring consistent measurement precision even as the number of converters increases.
Data Source
AI summary
A power management integrated circuit including: a clock generator that generates an input clock; a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter; a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter; and a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter, wherein the first phase, the second phase and the third phase have different phases from each other.