PMIC Timekeeping Architecture for Secure Power-Off Time Integrity
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Solution Overview
Problem
Mobile devices face challenges in maintaining the integrity and security of time information due to potential alterations or tampering during power outages or malicious attacks, which are critical for security-based operations.
Innovation Solution
The electronic device incorporates a nonvolatile memory, a power management integrated circuit, and an application processor to generate and manage time information independently of power supply, ensuring integrity through a security processor that handles time data securely, even in system-off states, using a read-only timer and power capacitor for auxiliary power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If time information is stored in a mobile device using standard power supply dependency, then the device can operate normally during powered states, but the time information may be altered or lost during power outages or system-off states
Solution Approach 1:
The patent segments the time information storage function into two independent components: a first timer in the power management integrated circuit that operates independently of supply power, and a second timer in the application processor that operates during powered states. This segmentation allows each timer to maintain time information under different power conditions, ensuring continuous reliable timekeeping without requiring a completely complex redundant system.
Solution Approach 2:
The patent introduces nonvolatile memory as an intermediary storage medium that receives and preserves time information from both timers. This intermediary component bridges the gap between the two timer systems, allowing time data to be safely stored and transferred between powered and unpowered states without loss or tampering, thus maintaining integrity while managing system complexity.
2Reliability
If a read-only timer is used to generate time information independently of supply power, then time integrity during power outages is maintained, but additional hardware components are required
Solution Approach 1:
The patent merges the read-only timer function into the power management integrated circuit, combining power management responsibilities with time information generation. This integration allows the first timer to operate independently using auxiliary power from the PMIC during system-off states, maintaining time integrity without requiring a completely separate hardware subsystem. The merging reduces overall device complexity while achieving the desired reliability.
3Reliability
If time information is continuously updated and stored in nonvolatile memory, then accurate time data is maintained across power cycles, but power consumption increases
Solution Approach 1:
The patent implements periodic action by having the application processor update time information from nonvolatile memory only when transitioning from a powered-off state to a powered-on state. During normal operation, the second timer continues generating time information without requiring frequent writes to nonvolatile memory. This periodic updating approach maintains accurate time data across power cycles while minimizing unnecessary power consumption from memory write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures the integrity and security of time information by maintaining accurate time data across power interruptions, reducing the risk of tampering and ensuring reliable security operations.
Implementation Method 1
a power management integrated circuit including a power capacitor configured to provide auxiliary power based on pre-charged electric charges in response to occurrence of a system-off state
Data Source
AI summary
Provided are an electronic device and an operating method thereof. The electronic device includes a nonvolatile memory; a power management integrated circuit configured to generate operating power based on supply power received from a power source, and generate first time information independent of the supply power; and an application processor configured to receive the operating power, generate second time information, obtain, based on the generation of the operating power being interrupted, the first time information, and output, to the nonvolatile memory, time data including the first time information and the second time information, a write command, and an address.