PMOS-Compensated Buffer Circuit for Stable Trigger Voltage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The trigger point voltage of digital buffers varies widely due to defective transistors, failing to meet requirements for low latency in integrated circuits.

Innovation Solution

A buffer apparatus with a voltage adjustment module using a P-type metal-oxide-semiconductor field-effect transistor (PMOS) to adjust input voltage based on a threshold voltage, coupled with a buffer module to stabilize the trigger point voltage, reducing its range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If Schmitt trigger circuits are used to implement digital buffers, then low latency is guaranteed, but the trigger point voltage varies widely due to defective transistors

Engineering Contradiction:
ImprovelatencyVSAvoidtrigger point voltage stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

A voltage adjustment module is introduced as an intermediary between the power supply and the Schmitt trigger circuit. This module includes a first PMOS transistor and associated circuitry that adjusts the drive voltage based on the threshold voltage of the PMOS transistor, thereby stabilizing the trigger point voltage of the buffer without increasing latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the drive voltage parameter dynamically by using the threshold voltage of the first PMOS transistor as a reference. The voltage adjustment module modifies the supply voltage to compensate for transistor defects, ensuring the trigger point voltage remains within the required range while maintaining the low-latency performance of the Schmitt trigger circuit.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If digital buffers are powered directly by supply voltage, then device complexity is reduced, but manufacturing precision requirements cannot be met due to wide trigger point voltage variation

Engineering Contradiction:
Improvebuffer structureVSAvoidtrigger point voltage control
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The voltage adjustment module uses the first PMOS transistor's own threshold voltage as a reference for adjustment. The gate of the first PMOS is connected to its drain, creating a self-regulating mechanism that automatically compensates for manufacturing variations in the transistor characteristics, thereby meeting precision requirements without requiring external calibration.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The voltage adjustment module serves as an intermediary that bridges the gap between the supply voltage and the buffer circuit. It includes compensation circuitry that actively adjusts the drive voltage to counteract manufacturing variations, enabling precise trigger point voltage control while keeping the overall device complexity manageable.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution narrows the range of trigger point voltage, ensuring it meets process requirements and improving the buffer's performance by compensating for process corners.

Implementation Method 1

a voltage adjustment module comprising a first P-type metal-oxide-semiconductor field-effect transistor (PMOS), wherein the voltage adjustment module is configured to receive an input voltage, adjust the input voltage with a threshold voltage for the first PMOS, and output a drive voltage

Methodology Applied
Scientific EffectField-effect transistor conduction:

Data Source

PatentUS11936375B2Buffer apparatus, chip and electronic device
Publication Date: 2024.03.19 CHIPONE TECHNOLOGY (BEIJING) CO LTD
  • US11936375B2 patent drawing
  • US11936375B2 patent drawing

AI summary

A buffer apparatus, a chip and an electronic device. The apparatus comprises: a voltage adjustment module (10) comprising a first P-type metal-oxide-semiconductor field-effect transistor (PMOS), wherein the voltage adjustment module (10) is used for receiving an input voltage, using a threshold voltage for the first PMOS to adjust the input voltage, and outputting a driving voltage; and a buffer module (20) electrically connected to the voltage adjustment module (10) and used for receiving an input signal, buffering the input signal under the driving voltage, and outputting a buffered signal. The driving voltage obtained by using the threshold voltage for the first PMOS to adjust the input voltage can compensate for a process corner of the buffer module (20), such that the range of a flip point voltage of the buffer module (20) becomes small and meets process requirements.