Nonvolatile Memory Cell Using PMOS and DMOS Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices using standard CMOS processes face limitations in increasing write and erase speed, leading to higher memory cell area and reduced data rewriting capacity, which affects reliability and cost-effectiveness.
Innovation Solution
A nonvolatile semiconductor memory device utilizing a plurality of MOS transistors sharing a floating gate, where one transistor employs channel capacitance for writing and depletion capacitance for erasure, enhancing write and erase efficiency by applying high bias for electron injection and low bias for emission through FN tunneling, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional standard CMOS process is used for nonvolatile memory, then manufacturing cost is reduced, but write and erase speed cannot be increased
Solution Approach 1:
The patent segments the gate function by using separate control gates (CG0, CG1) and erase gates (EG0, EG1) for different operations. This allows independent optimization of write and erase pathways, enabling high-speed operations while maintaining standard CMOS compatibility. The segmentation of charge injection and emission paths through different transistor gates resolves the speed limitation without requiring non-standard processes.
Solution Approach 2:
The patent employs dynamic control of transistor states through timed voltage applications to control gates. By dynamically switching between different gate configurations during write and erase operations, the system achieves high-speed performance. The dynamic manipulation of channel and depletion capacitances through controlled gating sequences enables rapid charge transfer while maintaining compatibility with standard CMOS manufacturing.
2Productivity
If write speed is increased, then data rewriting capacity increases, but memory cell area increases
Solution Approach 1:
The patent makes the floating gate serve multiple functions by using it as a shared charge storage element for both write and erase operations across multiple transistors. The control gates and erase gates are designed to universally control charge injection and emission from the same floating gate, enabling high data rewriting capacity without proportionally increasing memory cell area. This multi-functional design allows efficient space utilization.
Solution Approach 2:
The patent merges the charge storage function into a single floating gate that serves multiple transistors (NMOS and PMOS), rather than providing separate storage elements for each transistor. This consolidation allows high-speed rewriting capability to be achieved while minimizing the total memory cell area, as the shared floating gate structure reduces redundant components.
3Productivity
If erase speed is increased, then manufacturing efficiency improves, but minimum process size of erase gate transistor is limited
Solution Approach 1:
The patent introduces control gates (CG0, CG1) as intermediary elements that mediate between the erase gate voltage application and the floating gate charge removal. These control gates enable precise control of the erase process through capacitance coupling, allowing high-speed erase operations without requiring the erase gate transistor to be scaled to minimum process sizes. The intermediary gates provide the necessary control flexibility.
Solution Approach 2:
The patent changes the operational parameters of the erase process by using depletion capacitance coupling through control gates instead of direct gate control. By adjusting voltage parameters and timing sequences applied to multiple gates simultaneously, the system achieves high erase speed while maintaining transistor dimensions above the minimum process size, thus avoiding manufacturing precision limitations.
4Reliability
If threshold voltage in charge-0 state is decreased, then data retention characteristics improve, but excessive erasure occurs
Solution Approach 1:
The patent implements feedback control through the differential amplifier that monitors the stored charge state and provides feedback to the control gate voltages. This feedback mechanism prevents excessive erasure by automatically adjusting the erase gate voltage application based on the actual charge state, ensuring the threshold voltage reaches but does not drop below the desired charge-0 state level. This maintains data retention characteristics while preventing over-erasure.
Solution Approach 2:
The patent applies partial erasure action through controlled voltage sequences to the control gates, rather than applying maximum erase voltage continuously. By using timed, partial voltage applications to CG0 and CG1 gates, the system achieves the necessary threshold voltage reduction for charge-0 state without causing excessive erasure that would compromise data retention. The controlled partial action prevents harmful over-erasure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases erase speed, reduces voltage requirements, and enhances data rewriting capacity, maintaining reliability while preventing excessive erasure and minimizing memory cell area expansion.
Implementation Method 1
one of the MOS transistors for writing uses coupling of channel capacitance for writing and one of the MOS transistors for erasure uses coupling of depletion capacitance for erasure
Implementation Method 2
one of the MOS transistors for writing uses coupling of channel capacitance for writing and one of the MOS transistors for erasure uses coupling of depletion capacitance for erasure
Data Source
AI summary
A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.