Transmission Gate Layout With Four Metal Zero Tracks
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in designing transmission gates with lower profiles that can be integrated into circuit layouts using fewer metal zero tracks while maintaining effective current control between PMOS and NMOS transistors.
Innovation Solution
The design incorporates first and second PMOS transistors, first and second NMOS transistors, and conductive paths between their gates and source-drain terminals, with at least one conductive path including a segment perpendicular to the metal zero segments, arranged using a total of four metal zero tracks to reduce profile height and facilitate integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If transmission gates are designed with traditional metal zero track arrangements, then current control between PMOS and NMOS transistors is maintained, but profile height increases and integration complexity increases
Solution Approach 1:
The patent reconfigures the metal zero track arrangement from a traditional vertical stacking approach to a horizontal distribution approach across four tracks. This dimensional reorganization allows the transmission gate to achieve lower profile height by spreading conductive paths laterally rather than vertically, directly resolving the contradiction between reduced height and maintained connectivity.
Solution Approach 2:
The transmission gate is segmented into distinct PMOS and NMOS transistor sections with separate gate control paths. By dividing the device into modular sections that can be independently routed across the four metal zero tracks, the design achieves compact vertical profile while maintaining complete electrical connectivity through distributed horizontal routing.
2Reliability
If more metal zero tracks are used, then current control and connectivity are improved, but device area and integration density decrease
Solution Approach 1:
Each of the four metal zero tracks serves multiple functions: they provide gate control signals to both PMOS and NMOS transistors, establish source-drain connectivity, and enable signal routing between different transistor sections. This multi-functional use of limited tracks achieves reliable current control without requiring additional dedicated tracks for each function, thereby reducing overall device area.
Solution Approach 2:
The patent merges the gate control paths and source-drain connectivity paths into the same four metal zero tracks. By combining multiple electrical functions into a unified track arrangement, the design achieves complete current control capability while minimizing the total number of tracks required, thus reducing device footprint and improving integration density.
Data Source
AI summary
A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.