PMOS Transistor Source/Drain Germanium Integration
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Solution Overview
Problem
Conventional semiconductor transistor devices face challenges in minimizing parasitic resistance, particularly in PMOS transistors, which limits current performance due to high external resistance components.
Innovation Solution
The use of a p-type thin liner and high germanium content in source/drain regions, with a germanium concentration of at least 80 atomic %, reduces external resistance components and maximizes channel hole mobility by introducing compressive strain, thereby decreasing channel, tip, and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor transistor devices are used, then manufacturing is simpler, but parasitic resistance is high which limits current performance
Solution Approach 1:
The patent changes the material composition parameter by incorporating high germanium content (at least 80 atomic %) in the source/drain regions and using p-type silicon germanium liners with varying germanium concentrations. This parameter change reduces parasitic resistance and enhances hole mobility, thereby improving current performance without complicating the manufacturing process.
Solution Approach 2:
The patent employs composite materials by combining silicon germanium liners with high germanium content source/drain regions. The liner layer contains silicon and germanium in specific ratios, while the source/drain regions contain at least 80 atomic % germanium. This composite structure reduces parasitic resistance and improves transistor performance.
2Productivity
If device scaling is pursued to improve performance, then transistor density increases, but external resistance components become more significant
Solution Approach 1:
The patent changes the material composition parameter by incorporating high germanium content (at least 80 atomic %) in the source/drain regions and using p-type silicon germanium liners with varying germanium concentrations. This parameter change reduces parasitic resistance and enhances hole mobility, thereby improving current performance without complicating the manufacturing process.
3Object-affected harmful factors
If germanium content is increased to reduce resistance, then external resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The patent changes the material composition parameter by incorporating high germanium content (at least 80 atomic %) in the source/drain regions and using p-type silicon germanium liners with varying germanium concentrations. This parameter change reduces parasitic resistance and enhances hole mobility, thereby improving current performance without complicating the manufacturing process.
Solution Approach 2:
The patent uses an intermediary approach by employing a p-type silicon germanium liner layer between the substrate and the high germanium content source/drain regions. The liner acts as a mediator that facilitates the integration of high germanium content material while managing the manufacturing complexity through controlled germanium concentration gradients.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor current for a given voltage, improving overall transistor performance and supporting device scaling by reducing external resistance and short channel effects.
Implementation Method 1
maximizes channel hole mobility by introducing compressive strain, thereby decreasing channel, tip, and contact resistance
Data Source
AI summary
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.