PMOS High-Side Switch Gate Control for Voltage Oscillation Damping
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Solution Overview
Problem
Integrated circuit chips with PMOS transistor switches experience voltage oscillations on the source of the PMOS transistor during switching to the off state, due to parasitic inductors in the conductive wires connecting the chip to external power and reference voltages.
Innovation Solution
The integrated circuit chip incorporates a detection circuit to monitor the drain-source resistance of the PMOS transistor and a control circuit that supplies a first current during the initial phases of switching and a second, lower current during the final phase, ensuring complete discharge of parasitic inductors and minimizing voltage oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a PMOS transistor switch is used to couple an internal node to the connection pad connected to external power supply voltage, then the chip can function as a high-side switch in a DC-DC converter, but voltage oscillations occur on the source of the PMOS transistor during switching to the off state due to parasitic inductance of the conductive wire
Solution Approach 1:
The control circuit performs preliminary action by supplying a first current to the gate of the PMOS transistor before the switching event to ensure the transistor is fully enhanced and ready for rapid switching. This preliminary enhancement reduces the switching time while controlling the voltage oscillations caused by parasitic inductance.
Solution Approach 2:
The control circuit dynamically adjusts the gate current in two stages: first supplying a higher first current during the initial switching phase to achieve fast transition, then switching to a lower second current after detection of the switching event. This dynamic current adjustment optimizes both switching speed and voltage stability.
2Ease of manufacture
If a conductive wire is used to connect the connection pad to the external power supply voltage, then the chip can be powered externally, but the parasitic inductor of the conductive wire causes voltage oscillations during PMOS transistor switching
Solution Approach 1:
The detection circuit provides feedback by monitoring the drain-source resistance of the PMOS transistor and generating a detection signal that indicates when switching to the off state has occurred. This feedback enables the control circuit to adjust the gate current timing and magnitude, thereby reducing voltage oscillations caused by the parasitic inductance of the conductive wire.
Solution Approach 2:
The control circuit acts as an intermediary between the power supply and the PMOS transistor, mediating the switching process by controlling the gate current in two stages. This intermediary control reduces the impact of parasitic inductance on voltage oscillations while maintaining the simplicity of the conductive wire connection.
3Speed
If the control circuit supplies a high current to the gate of the PMOS transistor during switching to the off state, then the switching speed is improved, but the voltage oscillations on the source of the PMOS transistor increase due to parasitic inductance
Solution Approach 1:
The gate current is segmented into two distinct phases: a first current supplied during the initial switching phase to achieve fast transition, and a second current supplied after the switching event is detected. This segmentation allows the system to achieve high switching speed while minimizing voltage oscillations by reducing the current after the critical switching moment.
Solution Approach 2:
The control circuit employs periodic action by switching between two current levels based on the detection signal. The first current is supplied during the critical switching period, then the second current is supplied after detection of the switching event, creating a periodic current pattern that optimizes both speed and stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces or eliminates voltage oscillations on the PMOS transistor source, enhancing the reliability and longevity of the chip by preventing damage from excessive voltage peaks.
Implementation Method 1
a decoupling capacitor coupling the first and second connection pads together
Implementation Method 2
a diode coupling the internal node to the second connection pad, wherein the anode of the diode is on the side of the second connection pad
Data Source
AI summary
An integrated circuit chip includes a first pad coupled to an external power supply voltage by a conductive wire; a PMOS transistor coupling the first pad to an internal node; a second pad coupled to an external reference voltage by another conductive wire; and a capacitor coupling said first and second pads. A sensing circuit detects an increase in a drain-source resistance of the transistor. A control circuit supplies, during each switching of the transistor to the off state, a first current to the gate of the transistor until the sensing circuit detects the increase in the drain-source resistance, then supplies a second current lower than the first current.