PMOS High-Side Switch Control for Wire-Induced Voltage Oscillation
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Solution Overview
Problem
Integrated circuit chips with PMOS transistors as high side switches in DC-DC converters experience tension oscillations on the PMOS transistor source due to parasitic inductance of the conductive wire, which can damage the transistors and affect converter performance.
Innovation Solution
The integrated circuit chip includes a PMOS transistor coupled to a load through an internal node, a decoupling capacitor between supply and reference voltage studs, and detection and control circuits to manage the switching of the PMOS transistor, providing different currents during different phases of switching to minimize oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the PMOS transistor is switched to the off state, then the DC-DC converter operation is enabled, but voltage oscillations occur on the PMOS transistor source due to parasitic inductance of the conductive wire
Solution Approach 1:
The control circuit proactively supplies a first current to the gate of the PMOS transistor during the switching transition phase, before the transistor fully turns off. This preliminary action ensures that the transistor's resistance increases gradually, allowing the parasitic inductance to discharge its energy through the transistor rather than creating voltage oscillations when the transistor suddenly opens.
Solution Approach 2:
The control circuit dynamically changes the current supplied to the PMOS gate based on the transistor's resistance state. When the resistance is below a threshold, a first current is supplied to accelerate resistance increase. When the resistance exceeds the threshold, a second current (lower than the first) is supplied to maintain controlled discharge. This parameter change strategy optimizes the switching process to minimize voltage oscillations.
2Power
If a PMOS transistor is used as a high-side switch in a DC-DC converter, then power conversion is achieved, but the parasitic inductance of the conductive wire causes voltage oscillations that can damage the transistor
Solution Approach 1:
The control circuit prepares the PMOS transistor for the upcoming switching event by controlling the gate current in advance. During the transition phase, the circuit supplies a higher current to rapidly increase the transistor's resistance, creating a cushioning effect that absorbs the energy from the parasitic inductance before it can cause damaging voltage oscillations.
Solution Approach 2:
The control circuit acts as an intermediary between the power conversion function and the transistor switching. It mediates the switching process by dynamically adjusting the gate current based on the transistor's resistance state, ensuring that the energy from parasitic inductance is safely dissipated through the transistor rather than creating harmful voltage spikes.
3Speed
If the PMOS transistor resistance increases rapidly during switching, then the switching speed is improved, but voltage oscillations are generated due to parasitic inductance
Solution Approach 1:
The control circuit dynamically adjusts the gate current based on the real-time resistance state of the PMOS transistor. During the transition phase, a higher current is supplied to rapidly increase resistance and improve switching speed. Once the resistance exceeds a threshold, the current is reduced to a lower level to maintain the resistance increase while preventing voltage oscillations. This dynamic control strategy optimizes both switching speed and oscillation suppression.
Solution Approach 2:
The control circuit implements a two-stage periodic current supply strategy during the switching transition. The first stage supplies a higher current to rapidly increase transistor resistance, and the second stage supplies a lower current to maintain controlled discharge. This periodic action pattern enables fast switching while minimizing voltage oscillations caused by parasitic inductance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces or eliminates tension oscillations on the PMOS transistor source, preventing damage and ensuring stable operation of the DC-DC converter, without requiring modifications to the parasitic inductances or capacitance values.
Implementation Method 1
a decoupling capacitor coupling the first and second pads together
Implementation Method 2
a first detection circuit configured to detect an increase, for example above a first threshold, of a source/drain resistance of the PMOS transistor
Data Source
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AI summary
This description relates to an integrated circuit chip (200) comprising: a pad (102) coupled to an external supply voltage (Vin) by a conductive wire (106); a PMOS transistor (HS) coupling the pad (102) to an internal node (114); another pad (108) coupled to an external reference voltage (GND) by another conductive wire (112); a capacitor (C) coupling said pads (102; 108); a circuit (DET1) for detecting an increase in the source/drain resistance of the transistor; and a circuit (HS-CTRL') providing, during each switching to the blocked state of the transistor, a first current to the gate of the transistor until an increase in the source/drain resistance is detected, then a second current smaller than the first current.