PMOS Maximum Voltage Selector With Dynamic N-Well Biasing
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Solution Overview
Problem
Existing solutions for eliminating latch-up effects and minimizing channel resistance in MOS transistors are challenging due to difficulties in efficiently biasing the n-well regions of PMOS devices, particularly when dealing with separate power supplies that can lead to leakage, latch-up, forward-biased parasitic diodes, floating outputs, and excessive voltage drops.
Innovation Solution
A power supply switching circuit and method that uses a comparator, active power supply switching circuit, and gate driver circuit to remap first and second independent voltage supplies, ensuring the n-well of PMOS power switches is biased to the maximum possible voltage, preventing forward-biased junction diodes and minimizing resistance, without requiring special fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the n-well is permanently connected to the highest system voltage to prevent parasitic diode conduction, then latch-up is prevented, but the ON resistance of the PMOS device significantly increases due to reverse body bias
Solution Approach 1:
The patent implements dynamic n-well biasing by switching the n-well connection between the highest voltage supply and the source terminal based on the operating state. When the PMOS is OFF, the n-well is connected to the highest voltage to prevent latch-up. When the PMOS is ON, the n-well is connected to the source terminal to minimize body effect and reduce channel resistance. This dynamic switching resolves the contradiction between latch-up prevention and low resistance operation.
2Reliability
If the n-well is connected to the highest voltage to prevent forward-biased parasitic diodes, then device reliability improves, but design complexity and area increase due to larger device dimensions required to compensate for increased resistance
Solution Approach 1:
The patent uses dynamic switching of the n-well bias voltage to maintain low resistance during ON state while ensuring parasitic diode control during OFF state. This eliminates the need for permanently oversized devices, thereby reducing the required device area and design complexity while maintaining both reliability and performance.
3Adaptability or versatility
If separate power supplies are used for different voltage levels, then system versatility is improved, but leakage currents and latch-up risks increase due to improper n-well biasing
Solution Approach 1:
The patent implements dynamic n-well biasing that automatically adapts to the active power supply configuration. By switching the n-well connection based on which PMOS device is conducting, the circuit maintains proper biasing across different voltage levels and prevents leakage currents while supporting versatile multi-voltage operation.
Solution Approach 2:
The patent uses the state of the PMOS devices (conducting or non-conducting) to control the n-well biasing configuration. This feedback mechanism ensures that the n-well is always biased appropriately relative to the active device, preventing leakage currents and latch-up while supporting versatile power supply configurations.
4Object-affected harmful factors
If the n-well biasing is optimized for low resistance during ON state by connecting to source, then channel resistance decreases, but parasitic diodes may become forward-biased when the device is OFF
Solution Approach 1:
The patent dynamically switches the n-well biasing configuration based on the operating state of the PMOS device. During ON state, the n-well is connected to the source terminal to minimize body effect and reduce channel resistance. During OFF state, the n-well is connected to the highest voltage supply to ensure parasitic diodes remain reverse-biased. This dynamic switching resolves the contradiction between low resistance and parasitic diode protection.
Data Source
AI summary
A power supply switching circuit (100) and methodology are disclosed for connecting the greater of first and second power supplies (VSUP1, VSUP2) to an output voltage node (VOUT) with a comparator (102), active power supply switching circuit (103), gate driver circuit (106), and switching array (SW1-SW5) to generate control signals for a pair of PMOS power switches (MP1, MP2) by remapping first and second voltage supplies (VSUP1, VSUP2) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit (106) only in response to a comparator activation signal by generating overlapping phase signals (PHI_1, PHI_2) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.