PMOS Maximum Voltage Selector With Dynamic N-Well Biasing
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Solution Overview
Problem
Existing solutions for eliminating latch-up effects and minimizing channel resistance in MOS transistors are challenging due to difficulties in efficiently biasing the n-well regions of PMOS devices, especially in systems with separate power supplies, leading to issues like leakage, latch-up, forward biased parasitic diodes, and excessive voltage drops.
Innovation Solution
A power supply switching circuit that uses a comparator, active power supply switching circuit, and gate driver circuit to remap first and second independent voltage supplies, ensuring the n-well of PMOS power switches is biased to the maximum possible difference, preventing forward biased junction diodes and minimizing resistance, without requiring special fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the n-well is permanently connected to the highest system voltage to prevent parasitic diodes from turning ON, then latch-up prevention is improved, but the ON resistance of the PMOS device significantly increases due to reverse body bias
Solution Approach 1:
The patent applies dynamics by making the n-well biasing configuration switchable between two states: permanently connecting the n-well to the highest voltage when latch-up prevention is critical, and dynamically connecting the n-well to the source terminal when minimizing ON resistance is the priority. This dynamic reconfiguration allows the system to adapt to different operational requirements.
Solution Approach 2:
The patent changes the biasing parameter of the n-well from a fixed highest voltage connection to a variable connection that can be either the highest voltage or the source voltage depending on operational mode. This parameter change enables optimization of either latch-up prevention or ON resistance based on system needs.
2Reliability
If the n-well is connected to the highest system voltage, then parasitic diode conduction is prevented, but the area of the PMOS device must be increased to compensate for higher resistance
Solution Approach 1:
The patent uses dynamic switching to change the n-well connection from the highest voltage to the source voltage when the PMOS device needs to be in ON state. This dynamic reconfiguration reduces the body effect and allows smaller device area while maintaining acceptable resistance levels.
Solution Approach 2:
The patent changes the n-well bias voltage parameter from the highest system voltage to the source voltage, which reduces the voltage difference across the body junction and thereby reduces the body effect, allowing for smaller device area.
3Productivity
If the n-well biasing is optimized for one voltage mode, then performance in that mode is improved, but performance in other voltage modes deteriorates
Solution Approach 1:
The patent implements a dynamic control mechanism that switches the n-well biasing configuration based on the operational mode. When the PMOS needs to switch between different voltage modes, the control circuit dynamically reconfigures the n-well connection to maintain optimal performance across all modes.
Solution Approach 2:
The patent creates a universal n-well biasing solution that can handle multiple voltage modes and operational scenarios. The biasing circuit is designed to adapt to different voltage conditions, making the PMOS device versatile for various applications rather than optimized for a single mode.
Data Source
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AI summary
A power supply switching circuit (100) and methodology are disclosed for connecting the greater of first and second power supplies (VSUP1, VSUP2) to an output voltage node (VOUT) with a comparator (102), active power supply switching circuit (103), gate driver circuit (106), and switching array (SW1-SW5) to generate control signals for a pair of PMOS power switches (MP1, MP2) by remapping first and second voltage supplies (VSUP1, VSUP2) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit (106) only in response to a comparator activation signal by generating overlapping phase signals (PHI_1, PHI_2) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.