PN-Structured Gate Demodulation Pixel for 3D Imaging
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Solution Overview
Problem
Existing photo-detection devices in the charge domain, such as pinned photodiodes and MOS gate structures, face inefficiencies in charge transport due to lack of effective lateral electric fields, especially in larger pixel sizes, leading to slow charge movement and high power consumption in gate-based solutions, and inflexibility in drift voltage control in PPD-based methods.
Innovation Solution
The creation of a demodulation pixel using a PN-Structured Gate, where a poly-silicon gate with p-n junctions is used to generate electric drift fields, allowing for CCD-like control of voltage distribution and efficient charge transport without the need for narrow gates or overlapping structures, thereby avoiding potential bumps and step-wise potential gradients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single high-resistive gate is used to create lateral drift field, then charge transport speed is improved, but power consumption increases due to permanent resistive losses
Solution Approach 1:
The patent applies periodic action by using alternating high and low resistive gate regions that are dynamically switched. During the integration phase, the high-resistive region creates the drift field for charge transport, while during the reset phase, the low-resistive region allows charge removal. This periodic switching enables efficient charge transport only when needed, eliminating permanent resistive losses and reducing overall power consumption.
2Productivity
If several adjacent gates are used to form gate chain, then charge transport efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the gate structure into distinct high-resistive and low-resistive regions within a single gate electrode, rather than using multiple separate gates. This segmentation is achieved through selective doping or material composition in different portions of the same gate, creating the necessary potential gradient for efficient charge transport while simplifying the overall device architecture and reducing fabrication complexity.
Solution Approach 2:
The patent merges multiple gate functions into a single gate structure by combining both high-resistive and low-resistive regions in one gate electrode. This unified structure performs the functions of multiple gates (charge transport during integration and charge removal during reset) simultaneously, reducing device complexity while maintaining charge transport efficiency.
3Ease of operation
If transfer gate is set to high potential for charge transfer, then charge transport is enabled, but lateral electric field support is lost leading to slow thermal movement
Solution Approach 1:
The patent applies local quality by creating spatially varying resistive properties within the gate structure. The high-resistive region is positioned to create the lateral drift field where needed for charge transport, while the low-resistive region is positioned to enable efficient charge removal. This local differentiation of gate properties allows simultaneous optimization of both charge transfer capability and charge movement speed in different spatial zones.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient charge transport with flexible drift voltage control, reducing power consumption and improving charge handling efficiency while maintaining sensitivity, by creating a continuous electric field distribution without the drawbacks of traditional PPD or gate-based methods.
Implementation Method 1
a gate layer over the substrate having one or more p-n junctions
Implementation Method 2
a poly-silicon gate with p-n junctions is used to generate electric drift fields
Implementation Method 3
the pinned region 14 defines the photo-sensitive area 24 where photons are converted into electric charges
Data Source
AI summary
A novel photo-sensitive element for electronic imaging purposes and, in this context, is particularly suited for time-of-flight 3D imaging sensor pixels. The element enables charge-domain photo-detection and processing based on a single gate architecture. Certain regions for n and p-doping implants of the gates are defined. This kind of single gate architecture enables low noise photon detection and high-speed charge transport methods at the same time. A strong benefit compared to known pixel structures is that no special processing steps are required such as overlapping gate structures or very high- ohmic poly-silicon deposition. In this sense, the element relaxes the processing methods so that this device may be integrated by the use of standard CMOS technology for example. Regarding time-of-flight pixel technology, a major challenge is the generation of lateral electric fields. The element allows the generation of fringing fields and large lateral electric fields.