Anti-Serial PN-Junction Structure for Third Harmonic Suppression
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Solution Overview
Problem
Current semiconductor devices, such as ESD protection and TVS devices, generate spurious odd harmonics, particularly third harmonics, which interfere with other frequency bands, and existing approaches to minimize odd harmonics are insufficient, especially in reducing breakdown voltage while maintaining desired harmonic suppression.
Innovation Solution
The semiconductor device incorporates multiple pairs of anti-serially connected pn-junction structures with adjusted junction grading coefficients, specifically within a tolerance range defined by an ellipse equation, to minimize the generation of spurious odd harmonics, including the third harmonic, and achieve a desired breakdown voltage by optimizing the junction grading coefficients and capacitance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional pn-junction structures with standard junction grading coefficients are used, then the device provides basic ESD protection and TVS functionality, but the generation of spurious odd harmonics (particularly third harmonics) is not sufficiently suppressed
Solution Approach 1:
The patent applies parameter changes by adjusting the junction grading coefficients (m1, m2) of the pn-junction structures to specific values within defined ranges (m1: 0.40-0.60, m2: 0.15-0.35) to minimize the generation of spurious odd harmonics. This optimization of electrical parameters directly addresses the harmful harmonic generation while maintaining protective functionality.
Solution Approach 2:
The patent employs a composite structure consisting of multiple pn-junction structures (first pair with coefficient m1, second pair with coefficient m2) with different grading characteristics. This composite approach combines structures with different electrical properties to achieve superior harmonic suppression that cannot be obtained with a single uniform junction type.
2Object-generated harmful factors
If the junction grading coefficients are adjusted to suppress odd harmonics, then the harmonic generation is reduced, but the breakdown voltage control becomes more challenging
Solution Approach 1:
The patent simultaneously optimizes multiple parameters (junction grading coefficients m1 and m2, capacitance values Cj01 and Cj02) to achieve both harmonic suppression and breakdown voltage control. The specific parameter ranges defined in the patent enable balanced optimization of both performance aspects.
Solution Approach 2:
The patent employs simulation and measurement feedback to determine the optimal junction grading coefficients. By comparing the generated third harmonic power level against target specifications, the design parameters are iteratively adjusted to achieve both harmonic suppression and desired breakdown voltage characteristics.
3Device complexity
If a single pair of anti-serially connected pn-junction structures is used, then the device structure is simple, but the suppression of odd harmonics is insufficient
Solution Approach 1:
The patent divides the protection function into multiple independent pn-junction pairs, each with optimized grading coefficients. The first pair (m1) and second pair (m2) are segmented to perform different functions in the harmonic suppression mechanism, allowing each segment to be optimized for its specific role.
Solution Approach 2:
The patent creates a composite multi-pair structure where different pn-junction pairs with distinct grading coefficients work together. This composite architecture combines the protective functions of multiple junction types to achieve superior odd harmonic suppression compared to a single uniform pair.
Data Source
AI summary
A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.