POL Package Structure Eliminating Ceramic Substrates

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Solution Overview

Problem

Existing semiconductor device packaging methods face challenges with encapsulants having poor fracture toughness and high moisture sensitivity, leading to reliability issues, high costs, and limitations in miniaturization due to the use of ceramic substrates.

Innovation Solution

A POL package structure with dielectric layers that do not flow during lamination and dielectric sheets that melt and flow to fill gaps, forming all electrical and thermal interconnections, eliminating the need for ceramic substrates and reducing package thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If encapsulants and embedding compounds are used to protect semiconductor devices, then device protection is achieved, but reliability deteriorates due to poor fracture toughness and high moisture uptake

Engineering Contradiction:
Improvedevice protectionVSAvoidencapsulant reliability
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent removes the encapsulant/embedding compound layer entirely from the package structure. Instead of using traditional encapsulants that have poor fracture toughness and high moisture uptake, the invention uses a laminate structure with dielectric layers and curable dielectric sheets that cure to form a robust protective structure without the reliability issues of conventional encapsulants

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a composite laminate structure consisting of dielectric layers and curable dielectric sheets. This composite construction provides both mechanical protection and environmental sealing, achieving device protection while maintaining high reliability through the superior fracture toughness and low moisture uptake characteristics of the laminate materials

Inventive Principle:
Principle #40Composite materials

2Object-affected harmful factors

If encapsulants and embedding compounds are used to protect semiconductor devices, then device protection is achieved, but manufacturing cost increases and manufacturing time increases

Engineering Contradiction:
Improvedevice protectionVSAvoidmanufacturing cost and time
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent eliminates the separate encapsulant application process by integrating protective functionality into the laminate structure itself. The dielectric layers and curable dielectric sheets are applied directly during the laminate construction process, removing the need for separate encapsulant procurement and application steps, thereby reducing both material costs and manufacturing time

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of operation

If ceramic substrates are used in POL packages for electrical and thermal connectivity, then device connectivity is achieved, but package size and thickness increase, limiting miniaturization

Engineering Contradiction:
Improveelectrical and thermal connectivityVSAvoidpackage thickness
Core Design Contradiction:
Ease of operationVSLength of stationary object

Solution Approach 1:

The patent removes the ceramic substrate from the package structure entirely. Instead of using a separate ceramic substrate for electrical and thermal connectivity, the invention integrates these functions directly into the laminate structure through copper foil layers and conductive vias formed within the dielectric layers, eliminating the thickness contribution of ceramic substrates and enabling package miniaturization

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The laminate structure serves multiple functions simultaneously: it provides mechanical support, electrical connectivity through copper foils and vias, thermal management pathways, and environmental protection. This multi-functional integration eliminates the need for separate ceramic substrates while maintaining all necessary connectivity functions

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Ease of operation

If soldering operations are used to connect POL sub-modules to ceramic substrates, then electrical and thermal connectivity is achieved, but manufacturing cost increases and manufacturing time increases

Engineering Contradiction:
Improveelectrical and thermal connectivityVSAvoidmanufacturing cost and time
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The patent merges the connectivity function with the substrate structure itself. By forming copper interconnects directly within the laminate layers and on the laminate surfaces, the invention eliminates the need for separate soldering operations to attach components to a ceramic substrate. The laminate structure itself becomes the interconnection medium, reducing manufacturing steps and costs

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances reliability, reduces costs, and enables miniaturization by providing a surface-mount compatible package with double-sided cooling and robust interconnects, while eliminating the need for additional substrates and assembly processes.

Implementation Method 1

each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process

Methodology Applied
Scientific EffectMelting and flowing: Melting

Implementation Method 2

Metal interconnects are then electroplated onto the dielectric layer to form a direct metallic connection to the semiconductor device(s)

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9391027B2Embedded semiconductor device package and method of manufacturing thereof
Publication Date: 2016.07.12 GENERAL ELECTRIC CO
  • US9391027B2 patent drawing
  • US9391027B2 patent drawing
  • US9391027B2 patent drawing

AI summary

A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).