Polarization-Based Wafer Mapping for Fast Defect Localization
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Solution Overview
Problem
Existing methods for generating wafer maps in semiconductor fabrication rely on electron microscopes and structure models, which are slow and can damage the wafer, and suffer from issues like overfitting and model homeostasis due to limited sample sizes.
Innovation Solution
A wafer map generation device that uses a dimension reducer and map generator to process polarization matrices without electron microscopes or structure models, performing dimension reduction and mapping to generate high-speed wafer maps, allowing detection of abnormal process locations and improving yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If electron microscopes and structure models are used to generate wafer maps, then measurement precision is improved, but productivity deteriorates due to slow processing speed
Solution Approach 1:
The patent replaces the mechanical/electronic system of electron microscopes with an optical system using polarized light and matrix processing. Instead of using electron beams and complex microscope hardware, the invention uses light polarization matrices combined with dimension reduction algorithms to generate wafer maps, achieving both high speed and precision
Solution Approach 2:
The patent transforms the approach by changing from direct imaging to parameter-based processing. It uses polarization matrix parameters (psi and delta values) combined with dimension reduction techniques to extract wafer map information, enabling rapid processing while maintaining measurement accuracy
2Measurement precision
If electron microscopes are used to generate wafer maps, then measurement precision is improved, but object-affected harmful factors worsen due to wafer damage
Solution Approach 1:
The patent replaces the electron beam-based mechanical system with a non-contact optical system using polarized light. This substitution eliminates the harmful effects of electron beam exposure on the wafer while maintaining the ability to generate accurate wafer maps through matrix processing and dimension reduction
3Device complexity
If structure models with limited sample sizes are used, then device complexity is reduced, but reliability deteriorates due to overfitting and model homeostasis
Solution Approach 1:
The patent extracts the essential information from polarization matrices through dimension reduction, obtaining key parameters (psi and delta) that directly represent wafer characteristics. This extraction approach eliminates the need for complex structure models while improving reliability by working with fundamental optical parameters that are less prone to overfitting
Data Source
AI summary
A wafer map generation device includes a dimension reducer and a map generator. The dimension reducer is configured to receive a plurality of polarization matrices associated with a plurality of target positions of a target wafer substrate and to generate a plurality of reduction result data through dimension reduction of one or more elements of each of the plurality of polarization matrices. The map generator is configured to generate a wafer map associated with the target wafer substrate based on the plurality of reduction result data.