Low-Defect Polishing Pad with Tapered Land Support
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Solution Overview
Problem
Conventional poromeric polishing pads face challenges in achieving low defectivity and high TEOS removal rates, particularly in copper-barrier polishing applications, with existing pads often resulting in excessive foam and alkali metal contamination that can impair semiconductor performance.
Innovation Solution
A polishing pad with an open-cell polymeric matrix featuring vertical pores and grooves, including projecting land areas with tapered support structures, designed to optimize debris removal and reduce polishing dwell time, while being surfactant-free to prevent foam and contamination, and using a non-woven felt substrate to prevent air bubble trapping and enhance adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional poromeric polishing pads are used, then polishing can proceed, but excessive foam and alkali metal contamination occur that disrupt polishing and reduce semiconductor performance
Solution Approach 1:
The patent removes harmful surfactants and alkali metals from the polishing pad composition entirely. The pad is formulated without these substances that cause foam and contamination, extracting the harmful elements from the system while maintaining polishing functionality through the porous polyurethane structure and controlled pore architecture.
Solution Approach 2:
The patent changes the chemical composition parameters of the polishing pad by eliminating surfactants and alkali metals. This parameter change transforms the pad from a foam-generating, contaminating material to a clean, stable polishing surface that maintains process reliability and semiconductor performance.
2Productivity
If polishing pads with high TEOS removal rate are used, then material removal is efficient, but defectivity increases and low defectivity cannot be achieved
Solution Approach 1:
The patent applies local quality by creating different pore size regions and structural zones within the polishing pad. The porous structure provides high removal rate in material contact zones while maintaining low defectivity in polishing zones through controlled pore distribution and size variation, allowing simultaneous optimization of both productivity and precision.
Solution Approach 2:
The patent uses composite material structure combining porous polyurethane with specific pore architectures. This composite approach integrates high removal rate capabilities with low defectivity characteristics in a single pad system, achieving both efficient TEOS removal and low scratch/chattermark generation.
3Duration of action of moving object
If polishing pads with long polishing dwell time are used, then thorough polishing occurs, but debris accumulates and increases defectivity
Solution Approach 1:
The patent segments the polishing pad surface into distinct functional zones including polishing regions and debris ejection regions. This segmentation allows the pad to perform thorough polishing in contact zones while providing dedicated pathways for debris removal, preventing accumulation and reducing defectivity despite extended dwell time.
Solution Approach 2:
The patent utilizes fluid dynamics and pneumatic principles through the porous structure to facilitate debris ejection. The pore architecture creates fluid flow paths that actively remove debris from the polishing interface, preventing accumulation even during extended polishing dwell time and maintaining low defectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces defects and maintains stable removal rates for copper and TEOS, providing improved planarization and reduced chattermarks, enhancing the yield and performance of semiconductor wafers.
Implementation Method 1
an open-cell polymeric matrix having vertical pores and open channels interconnecting the vertical pores; a plurality of grooves in the polishing layer
Implementation Method 2
a plurality of projecting land areas within the plurality of grooves, the plurality of projecting land areas being buttressed with a tapered support structure that extends outward and downward from the bottom plurality of projecting land areas
Data Source
AI summary
The polishing pad is suitable for polishing or planarizing at least one of semiconductor, optical and magnetic substrates with a polishing fluid and relative motion between the polishing pad and the at least one of semiconductor, optical and magnetic substrates. The polishing layer has an open-cell polymeric matrix, a polishing surface, a plurality of grooves in the polishing layer. The plurality of projecting land areas are buttressed with a tapered support structure that extends outward and downward from the bottom plurality of projecting land areas. The plurality of projecting land areas have an average width less than average width of the plurality of grooves for decreasing polishing dwell time of the projecting land areas and increasing the debris removal dwell time of the groove areas to a value greater than the polishing dwell time.