Poly-Silicon and Oxide Semiconductor TFT Array Substrate
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Solution Overview
Problem
Current display technologies face challenges in achieving slim edge-frame designs, which limit the screen ratio and displaying performance due to larger non-display areas in display devices.
Innovation Solution
The development of an array substrate with a small size, featuring simultaneously formed thin-film transistors using poly-silicon and oxide semiconductor materials, reduces the size of thin-film transistors in pixels and driving circuits, thereby minimizing non-display areas and increasing the screen-to-surface ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional display technologies are used, then the display device can be manufactured, but the non-display area is large which limits the screen ratio
Solution Approach 1:
The patent changes the material parameters of the thin-film transistors by using oxide semiconductor materials (such as IGZO) instead of conventional materials. This material substitution enables smaller transistor dimensions while maintaining electrical performance, directly reducing the non-display area and increasing the screen ratio.
Solution Approach 2:
The patent employs a top-gate transistor structure where the gate electrode is positioned above the active layer rather than beside it. This vertical arrangement of the gate structure allows for more compact in-plane dimensions, contributing to reduced non-display area and larger screen ratio.
2Area of stationary object
If the thin-film transistor size is reduced to increase screen ratio, then the display area increases, but the manufacturing complexity increases
Solution Approach 1:
The patent uses a unified oxide semiconductor material system for both the active layer and gate electrode, allowing the same material deposition and processing techniques to be applied throughout. This universality simplifies the manufacturing process despite the reduced transistor size, as the same equipment and procedures can be used for multiple critical components.
Solution Approach 2:
The patent forms the oxide semiconductor active layer and gate electrode in a sequential manner using the same material system, where the active layer is deposited first, followed by the gate electrode. This preliminary arrangement of material deposition steps simplifies the overall manufacturing process by using consistent material handling procedures.
3Productivity
If oxide semiconductor materials are used for thin-film transistors, then the transistor size is reduced and screen ratio increases, but the manufacturing process becomes more complex
Solution Approach 1:
The patent utilizes oxide semiconductor materials that can be deposited at relatively low temperatures using sputtering or other physical vapor deposition techniques. This parameter change in deposition temperature and method makes the manufacturing process more compatible with existing display fabrication lines, easing the manufacturing complexity despite the advanced material system.
Solution Approach 2:
The patent employs oxide semiconductor materials that can be integrated with conventional display layer structures. The oxide semiconductor layer can be combined with standard insulation layers, electrode materials, and passivation layers, creating a composite structure that maintains ease of manufacture while achieving the benefits of smaller transistor size.
Data Source
AI summary
An array substrate and a manufacturing method thereof are provided. The array substrate includes a first thin-film transistor and a second thin-film transistor formed on a base and spaced from each other by a predetermined distance and set in parallel. The first thin-film transistor includes, sequentially stacked on the base, a first active layer, a first gate insulation layer, a first gate electrode, an interlayer insulation layer, and first source/drain electrodes. The first source/drain electrodes are electrically connected with the first active layer. The second thin-film transistors includes, sequentially stacked on the base, a second gate electrode, a second gate insulation layer, a second active layer, an etch stop layer, and second source/drain electrodes. The first active layer and the second gate electrode are both formed of a poly-silicon material. The first gate electrode and the second active layer are both formed of an oxide semiconductor material.