Polycrystalline Silicon TFT Active Layer Uniformity
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Solution Overview
Problem
Existing display devices, particularly active matrix type LCDs, face issues with thin film transistor performance due to thickness differences in the active layer caused by manufacturing processes, leading to degraded properties and low mobility, and the use of amorphous silicon limits their effectiveness, while polycrystalline silicon transistors increase production costs and complexity.
Innovation Solution
The method involves forming a gate electrode and active layer using extrinsic and intrinsic polycrystalline silicon, with a buffer layer and etch stopper to maintain uniformity and prevent damage during the dry-etching process, and using Solid Phase Crystallization (SPC) to crystallize amorphous silicon layers, reducing production costs and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used for the active layer, then manufacturing cost is reduced, but transistor mobility and electrical properties are degraded
Solution Approach 1:
The patent changes the material parameter from amorphous silicon to polycrystalline silicon, which fundamentally alters the electrical properties and mobility characteristics while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The patent employs a composite structure with multiple silicon layers (intrinsic and extrinsic polycrystalline silicon) with different properties, where the intrinsic layer provides high mobility and the extrinsic layer provides good contact properties
2Reliability
If the active layer thickness is increased to improve transistor performance, then electrical properties are enhanced, but manufacturing precision is degraded due to thickness variation
Solution Approach 1:
The patent performs preliminary crystallization of the amorphous silicon layer into polycrystalline silicon before subsequent processing, which establishes a uniform crystal structure that maintains thickness uniformity while providing high mobility
Solution Approach 2:
The patent changes the material state from amorphous to polycrystalline, which fundamentally improves the electrical properties and mobility while maintaining manufacturing feasibility
3Reliability
If ion implantation is used to create extrinsic silicon regions, then transistor performance is improved, but device complexity and production cost increase
Solution Approach 1:
The patent replaces the ion implantation process (mechanical/physical process) with an in-situ crystallization process that forms extrinsic silicon regions through Solid Phase Crystallization, eliminating the need for additional ion implantation equipment and process steps
Solution Approach 2:
The patent enables the silicon layer to self-organize into extrinsic regions through controlled crystallization, where the material itself performs the doping function without requiring external ion implantation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved thin film transistor performance with uniform thickness and enhanced mobility, reducing production costs and complexity by eliminating the need for ion implantation, and achieving better electrical properties compared to traditional amorphous silicon-based transistors.
Implementation Method 1
using Solid Phase Crystallization (SPC) to crystallize amorphous silicon layers
Data Source
AI summary
A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line.