Polycrystalline Semiconductor Grain Alignment for 3D Memory Integration
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the high cost of advanced equipment needed for fine pattern formation, hindering increased performance and affordability, prompting the development of three-dimensional semiconductor devices with vertically arranged memory cells.
Innovation Solution
A semiconductor device featuring a polycrystalline semiconductor layer with grain regions and grain boundaries on a substrate, including vertical channel structures and separation trenches, which allows for increased integration and capacity while maintaining good lattice characteristics through selective epitaxial growth and laser annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited due to area constraints and high equipment costs for fine pattern formation
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically arranged memory cells. The memory cells are stacked in the vertical direction (third dimension) with multiple layers including bit lines, word lines, and charge storage regions arranged vertically, thereby increasing integration without requiring finer lateral patterning and avoiding the need for expensive advanced lithography equipment.
2Productivity
If three-dimensional vertically arranged memory cells are implemented, then integration increases, but lattice defects and reliability issues arise due to grain boundaries in polycrystalline structures
Solution Approach 1:
The patent applies selective laser annealing to specific regions of the polycrystalline semiconductor layer to create grain regions with improved crystal orientation. By locally treating areas beneath vertical channel structures with laser energy, the crystal grains are reoriented with their longitudinal axes aligned parallel to the vertical channel structures, reducing grain boundary defects in critical areas and improving carrier transport and device reliability.
Solution Approach 2:
The patent utilizes laser annealing to change the thermal and structural parameters of the polycrystalline semiconductor layer. The laser heating temporarily raises the temperature and enables crystal grain reorientation, transforming the microstructure from random grain orientation to aligned grain orientation in selected regions, thereby improving electrical characteristics and reducing defects.
3Ease of manufacture
If grain boundary regions are present in the polycrystalline semiconductor layer, then material formation is easier, but defect density increases and vertical channel structure formation is hindered
Solution Approach 1:
The patent applies selective laser annealing to create localized grain regions with improved crystal orientation beneath vertical channel structures. The laser treatment is applied only to specific areas where vertical channels will be formed, reorienting crystal grains so their longitudinal axes align with the vertical channel direction. This local improvement reduces grain boundary defects in critical regions while maintaining the ease of polycrystalline layer formation overall.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of highly reliable, high-capacity semiconductor devices with improved integration and reduced defect density, facilitating the formation of efficient vertical channel structures and enhancing the overall performance and cost-effectiveness of three-dimensional semiconductor memory devices.
Implementation Method 1
selective epitaxial growth and laser annealing processes
Implementation Method 2
selective epitaxial growth and laser annealing processes
Data Source
AI summary
A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.