Through Polymer Via Formation in Ultra-Thin CoWoS Devices

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Solution Overview

Problem

Forming through silicon vias (TSVs) using existing via-first or via-middle processes is challenging and costly, hindering advancements in 3D integration technology.

Innovation Solution

The development of a Chip on Wafer on Substrate (CoWoS) device that employs a through polymer via (TPV) formed without an interlayer or isolation layer, using a single damascene electroplating process and without wafer thinning or chemical vapor deposition, with copper interconnects and microbumps for efficient electrical communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through silicon vias (TSVs) are formed using via-first or via-middle processes, then vertical interconnects are achieved for 3D integration, but manufacturing cost and process complexity increase significantly

Engineering Contradiction:

Improvevertical interconnect reliabilityVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the silicon interlayer from the traditional TSV formation process. By forming through polymer vias directly through the polymer interlayer without requiring silicon-based intermediate layers, the process complexity is reduced while maintaining the vertical interconnect function. This extraction of the silicon interlayer component simplifies the overall fabrication sequence.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the traditional approach by forming vias through the polymer interlayer first, then filling with copper, rather than forming silicon-based interlayers and vias sequentially. This inversion of the process sequence eliminates multiple deposition and etching steps, reducing manufacturing complexity while achieving the same vertical interconnect reliability.

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If traditional TSV formation processes are used, then vertical interconnects are achieved, but manufacturing cost increases by approximately 47%

Engineering Contradiction:

Improveelectrical communication reliabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces expensive silicon-based interlayer materials with polymer materials that are cheaper and easier to process. The polymer interlayer serves the same structural and insulating function but at lower material and processing cost, achieving the same electrical communication reliability without the high manufacturing expenses of traditional silicon-based TSV processes.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the material parameter from silicon-based interlayers to polymer-based interlayers, fundamentally altering the fabrication parameters. This material substitution enables simpler processing conditions, lower deposition temperatures, and reduced manufacturing steps, thereby decreasing production cost by approximately 47% while maintaining via reliability.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If wafer thinning and chemical vapor deposition are used in TSV formation, then precise via structures are achieved, but process complexity and manufacturing steps increase

Engineering Contradiction:

Improvevia structure precisionVSAvoidfabrication efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent extracts and eliminates the wafer thinning step from the fabrication process. By forming through polymer vias in the as-built wafer structure without requiring thinning, the manufacturing precision of via placement is maintained while significantly improving fabrication efficiency and reducing process steps.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces mechanical/chemical processes (wafer thinning, CVD) with a simpler electroplating-based approach. The electroplating process directly deposits copper through the polymer interlayer to form precise via structures without requiring prior wafer thinning or complex CVD sequences, thereby maintaining via precision while enhancing productivity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces manufacturing costs by approximately 47% and enables high-performance, ultra-thin CoWoS devices with improved electrical communication, addressing the cost and complexity issues of traditional TSV formation methods.

Implementation Method 1

performing a first electroplating process to generate a through polymer via in the first polymer layer using the first copper seed layer

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS8951838B2Low cost and ultra-thin chip on wafer on substrate (CoWoS) formation

Publication Date: 2015.02.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.