Polymeric Layer for Semiconductor Stack Thermal Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional RFCMOS SOI technologies face nonlinearities due to the high resistivity silicon wafer handle region interfaced with the buried oxide (BOX) dielectric region, leading to complex and costly mitigation solutions that are not effectively addressed.
Innovation Solution
A semiconductor device and manufacturing method that replaces the silicon wafer handle with a polymeric layer having high thermal conductivity and electrical resistivity, eliminating the need for high resistivity silicon handles and simplifying the process flow, while maintaining or improving electrical insulation and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high resistivity silicon wafer handle is used to maintain isolation between stacked FETs, then electrical insulation is improved, but nonlinearities and RF intermodulation increase
Solution Approach 1:
The patent changes the material parameter from high resistivity silicon to a polymer composite with high electrical resistivity and high thermal conductivity. This parameter change maintains the electrical insulation function while eliminating the nonlinearities associated with silicon/oxide interfaces, thereby resolving the contradiction between isolation and RF linearity.
Solution Approach 2:
The patent employs a composite material consisting of polymer matrix with thermally conductive filler particles. This composite achieves both high electrical resistivity (for isolation) and high thermal conductivity (for heat dissipation), while avoiding the harmful nonlinearities of traditional silicon handles.
2Object-generated harmful factors
If complex harmonic suppression techniques and trap rich layers are applied to mitigate nonlinearities, then RF linearity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and removes the source of nonlinearities by eliminating the high resistivity silicon wafer handle and its interface with the BOX layer. By taking out the problematic silicon/oxide interface, the need for complex harmonic suppression techniques and trap rich layers is eliminated, thereby reducing manufacturing complexity while maintaining RF linearity.
3Ease of manufacture
If conventional silicon wafer handles are used, then manufacturing experience is leveraged, but thermal dissipation efficiency is limited
Solution Approach 1:
The patent changes the thermal conductivity parameter from the limited thermal dissipation of silicon to the superior thermal conductivity of the polymer composite material. This enables more efficient heat dissipation while maintaining ease of manufacture through simplified processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves linear RF switch characteristics close to ideal, allows for higher RF power levels and frequencies, and reduces costs by eliminating the need for complex harmonic suppression techniques and trap rich layers, enabling more efficient voltage stacking and thermal dissipation.
Implementation Method 1
disposing a polymeric layer that includes a polymer and an admixture that increases thermal conductivity of the polymer onto the first surface of the semiconductor stack structure
Implementation Method 2
The polymeric layer has high thermal conductivity and high electrical resistivity
Data Source
AI summary
A method of manufacture for a semiconductor device is disclosed. The method includes providing a semiconductor stack structure that includes a device terminal of a semiconductor device, and having a first surface and a buried oxide (BOX) layer attached to a wafer handle. Another step includes disposing a polymeric layer that includes a polymer and an admixture that increases thermal conductivity of the polymer onto the first surface of the semiconductor stack structure. Another step involves removing the wafer handle from the BOX layer to expose a second surface of the semiconductor stack structure, and yet another step involves removing a portion of the semiconductor stack structure to expose the device terminal.