Polymeric Passivation Layer for Semiconductor Chip Stress Relief
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Solution Overview
Problem
Conventional semiconductor chip passivation structures require multiple complex and time-consuming steps, involving multiple material movements and chemical vapor deposition processes, which increase manufacturing time and complexity, and often involve separate facilities for different processing stages.
Innovation Solution
A monolithic polymeric passivation layer is applied to the semiconductor chip, which serves both as a protective layer and provides thermal mechanical stress relief, eliminating the need for a multi-layer laminate passivation structure and reducing processing steps by allowing conductor pad exposure through a single deposition and patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-layer laminate passivation structure with alternating silicon nitride and undoped silicate glass layers is used, then protection and thermal stress relief are provided, but the number of material movements and CVD processes increases significantly
Solution Approach 1:
The patent combines multiple separate passivation layers (silicon nitride and undoped silicate glass) into a single polymeric passivation layer. This merging of multiple protective functions into one integrated layer eliminates the need for alternating deposition processes and reduces the number of material movements while maintaining protection and thermal stress relief capabilities
Solution Approach 2:
The polymeric passivation layer is designed to perform multiple functions simultaneously: it provides mechanical protection, thermal stress relief, and electrical insulation. This multi-functional approach replaces the need for separate specialized layers, reducing process complexity while maintaining reliability
2Reliability
If a six layer stack of alternating silicon nitride and undoped silicate glass is applied, then adequate passivation and stress management are achieved, but manufacturing time and processing steps increase
Solution Approach 1:
The patent merges six separate deposition steps for alternating layers into a single polymeric layer application process. This consolidation dramatically reduces manufacturing time and processing steps while maintaining the essential passivation and stress management functions through the engineered properties of the polymeric material
3Manufacturing precision
If separate facilities are used for passivation structure formation and polyimide layer application, then specialized processing is achieved, but material handling and coordination complexity increase
Solution Approach 1:
The patent combines the functions of separate passivation structure formation and polyimide layer application into a single polymeric passivation layer that can be processed in one facility. This integration eliminates the need for wafer shipment between vendors and reduces coordination complexity while maintaining manufacturing precision through controlled single-facility processing
Data Source
AI summary
Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads.