Polymeric Stress Buffer for TSV Semiconductor Packages
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Solution Overview
Problem
The existing semiconductor package structures face issues with conductive bump cracking and dielectric film delamination due to thermal mismatch between the interposer and the circuit board, causing physical stress during thermal cycling, which affects the reliability of three-dimensional IC packages.
Innovation Solution
A semiconductor package structure is developed with a polymeric layer on the corner and edge regions as a stress buffer, which absorbs and disperses the stress caused by different thermal expansion, preventing conductive bump cracking and dielectric film delamination. The polymeric layer is strategically positioned around the conductive bumps and underlying dielectric materials to mitigate rotational shear and mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive bumps are disposed between the interposer and the circuit board to establish electrical connections, then electrical connectivity is achieved, but cracking occurs during cooling down due to thermal expansion mismatch
Solution Approach 1:
A polymeric layer is introduced as an intermediary material between the interposer and the circuit board, specifically positioned around the conductive bumps. This polymeric layer acts as a stress buffer that absorbs and disperses the thermal expansion mismatch stress, preventing crack propagation while maintaining electrical connectivity through the conductive bumps.
Solution Approach 2:
The patent modifies the mechanical properties of the interface region by introducing a polymeric material with different thermal expansion characteristics compared to the rigid interposer and circuit board. This parameter change in material composition creates a gradient that reduces stress concentration at the conductive bump interfaces during thermal cycling.
2Quantity of substance
If more devices are integrated into one chip to increase circuit density, then circuit density is improved, but design complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from traditional two-dimensional chip integration to a three-dimensional architecture using an interposer structure. The interposer provides additional vertical layers and routing dimensions, allowing signals and power to be distributed through multiple planes, thereby increasing circuit density without proportionally increasing planar footprint or design complexity.
3Reliability
If conductive bumps are positioned at edges or corners of the interposer to maximize connectivity, then electrical connections are optimized, but stress concentration increases leading to cracking
Solution Approach 1:
The polymeric layer is strategically positioned beforehand around the conductive bumps at edges and corners of the interposer, creating a cushioning effect. This pre-positioned polymeric material absorbs and disperses the stress that would otherwise concentrate at these vulnerable locations during thermal cycling, preventing crack initiation and propagation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polymeric layer effectively reduces the risk of conductive bump cracking and dielectric film delamination, enhancing the reliability and durability of the semiconductor package structure by absorbing and dispersing stress from thermal mismatch, thereby improving the thermal cycling performance and reliability of the package.
Implementation Method 1
conductive bumps disposed between the interposer and the circuit board are subject to shearing and stress, which results from the different thermal expansion due to different thermal coefficients
Implementation Method 2
A semiconductor package structure is developed with a polymeric layer on the corner and edge regions as a stress buffer, which absorbs and disperses the stress caused by different thermal expansion
Data Source
AI summary
A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.