Polymetal Gate Interface Resistance Reduction
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Solution Overview
Problem
The existing manufacturing methods for semiconductor devices with polymetal gate structures and dual-gate structures result in nonlinearly high interface resistance between barrier metal films and polycrystalline silicon films, leading to uneven performance in NMOS and PMOS transistors, affecting circuit operation.
Innovation Solution
A method involving selective ion-implantation of P-type and N-type impurities, followed by annealing and silicide film formation, then deposition of barrier and metal films, to stabilize impurity distribution and reduce interface resistance by maintaining high impurity concentration at the interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polymetal gate structure with barrier metal film and metal film laminated on polycrystalline silicon film is used, then the gate structure can achieve lower resistance than polycide gate structure, but the interface resistance between barrier metal film and polycrystalline silicon film becomes nonlinearly high
Solution Approach 1:
The patent applies preliminary action by performing selective ion-implantation of impurities into the polycrystalline silicon film before forming the barrier metal film. This pre-treatment modifies the electrical properties of the polycrystalline silicon at the interface region, preparing it to achieve lower interface resistance when the barrier metal is subsequently deposited.
Solution Approach 2:
The patent changes the electrical parameters of the polycrystalline silicon film by controlling impurity concentration through selective ion-implantation. By adjusting the type and concentration of impurities (P-type or N-type) in different regions, the patent optimizes the interface resistance characteristics to match the requirements of the overlying barrier metal film.
2Ease of manufacture
If conventional manufacturing method with simultaneous ion-implantation is used, then the process is simple, but the interface resistance of N-type and P-type polymetal gate electrodes cannot be simultaneously optimized
Solution Approach 1:
The patent segments the ion-implantation process into separate sequential steps for P-type and N-type impurities, rather than attempting simultaneous implantation. This allows independent optimization of impurity concentrations in different regions, enabling precise control of interface resistance for both N-type and P-type gate electrodes while maintaining manufacturing feasibility.
Solution Approach 2:
The patent performs preliminary ion-implantation of P-type impurities, followed by annealing, and then subsequent ion-implantation of N-type impurities. This sequential preliminary treatment of each impurity type allows independent optimization of each gate electrode's interface characteristics before barrier metal deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the interface resistance of both N-type and P-type polymetal gate electrodes, ensuring balanced transistor performance and preventing waveform delays in circuit operations, thereby enabling high-speed circuit operations.
Implementation Method 1
a second annealing, thereby discharging gas contained in the silicide film and activating the N-type impurities
Implementation Method 2
selective ion-implantation of P-type and N-type impurities
Implementation Method 3
forming a silicide film on the silicon film according to a CVD method
Data Source
AI summary
A silicon film is formed on a first region and a second region, respectively of a semiconductor substrate; P-type impurities are selectively ion-implanted into the silicon film in the first region; a first annealing is carried out, thereby the P-type impurities implanted in the silicon film are activated; N-type impurities are selectively ion-implanted into the silicon film in the second region, after the first annealing; a silicide film is formed on the silicon film according to a CVD method, after the ion-implantation of the N-type impurities; a second annealing is carried out, thereby gas contained in the silicide film is discharged and the N-type impurities are activated; a barrier metal film and a metal film are formed in this order on the silicide film; and the metal film, the barrier metal film, the silicide film and the silicon film are patterned, thereby a P-type polymetal gate electrode formed in the first region and an N-type polymetal gate electrode formed in the second region.