Polynomial Datapath Equivalence Verification in RTL Synthesis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current formal verification tools are limited in their ability to confirm the functional equivalence of complex or larger integrated circuit designs, often requiring excessive time or being insufficient for designs beyond a certain size or complexity.
Innovation Solution
The method involves recognizing polynomial datapath equivalence in Register Transfer Level (RTL) designs by restricting bit widths of internal signals to the largest output bit width, allowing for the comparison of modified designs to determine functional equivalence, thereby extending the applicability of formal verification tools to more complex designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is applied to complex or large designs, then verification confidence is improved, but verification time becomes excessively long or verification becomes infeasible
Solution Approach 1:
The patent segments the verification process into two distinct phases: (1) polynomial verification phase that checks algebraic properties of datapath operations, and (2) exhaustive simulation phase that verifies the remaining input space. This segmentation allows each phase to handle different aspects of verification efficiently, resolving the contradiction between verification completeness and time consumption
Solution Approach 2:
The patent changes the verification parameters by identifying polynomial datapath operations and applying algebraic simplification rules to reduce the input space. By transforming the verification problem from checking all possible inputs to checking only non-polynomial cases, the verification time is dramatically reduced while maintaining high confidence through the combination of polynomial verification and targeted simulation
2Reliability
If formal verification tools are used to verify equivalence of designs, then functional equivalence confidence is improved, but the tools are limited to small or simple designs only
Solution Approach 1:
The patent applies parameter changes by recognizing polynomial datapath operations and using algebraic properties to simplify the verification of large designs. By identifying operations that follow polynomial patterns (such as additions, multiplications, and linear transformations), the tool can verify equivalence of complex designs without being limited by size, thus resolving the contradiction between verification confidence and design complexity
Solution Approach 2:
The patent introduces an intermediary polynomial verification layer that bridges formal verification and simulation. This intermediary phase uses algebraic simplification to reduce complex design equivalence problems into manageable polynomial checks, enabling formal verification tools to handle large designs that would otherwise be intractable
Data Source
AI summary
A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted (52) to provide a first modified version of each of the designs. These first modified versions are compared each with the design from which it was derived in a comparison unit (54). The input bit widths of the data flow graph representation are then restricted to be no wider than the output bit widths (56) to derive second modified versions of the designs (58). These second modified versions are compared with each other (60) to determine which are equivalent. Equivalent designs can be passed to an RTL synthesis unit 62, or otherwise further evaluated.