Polynomial Multiplication Hardware Accelerator for Elliptic Curve Cryptography
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Solution Overview
Problem
Existing methods for polynomial multiplication in Galois fields, particularly in cryptographic applications, face challenges in area efficiency and energy consumption, limiting their use in mobile terminals due to high computation time and resource constraints.
Innovation Solution
An iterative method for polynomial multiplication that fragments polynomials into segments, allowing for partial multiplication with reduced calculation steps and controlled accumulation, resulting in a hardware implementation with lower area requirements and energy consumption, while maintaining performance in software implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If direct implementation of polynomial multiplication is used, then calculation accuracy is maintained, but chip area and energy consumption increase significantly
Solution Approach 1:
The patent divides the polynomial multiplication process into segments by fragmenting polynomials into smaller parts. Instead of computing the entire polynomial multiplication at once, the method processes segments iteratively, accumulating partial products. This segmentation reduces the simultaneous hardware resources needed, thereby reducing chip area while maintaining calculation accuracy through systematic accumulation of segment results.
2Reliability
If comprehensive cryptographic methods are used in mobile terminals, then security is improved, but resource consumption increases
Solution Approach 1:
The patent applies segmentation to cryptographic polynomial multiplication by breaking down large polynomial operations into smaller fragment multiplications. This reduces the computational burden and energy consumption per operation, making comprehensive cryptographic methods feasible for mobile terminals with limited energy resources while maintaining security through complete accumulation of partial results.
Solution Approach 2:
The patent implements partial multiplication of polynomial fragments rather than complete multiplication in each step. By performing partial multiplications and accumulating results iteratively, the method reduces energy consumption per computational step while achieving the same cryptographic security level through the complete accumulation process.
3Productivity
If hardware accelerators are implemented for cryptographic operations, then computation time is reduced, but chip area increases
Solution Approach 1:
The patent creates a hardware accelerator that processes polynomial multiplication through segmented iterative steps rather than requiring a complete parallel multiplication unit. By dividing the computation into fragment multiplications that can be processed sequentially with accumulation, the design achieves fast cryptographic computation while using significantly less chip area compared to full parallel hardware accelerators.
Solution Approach 2:
The patent implements a dynamic computation approach where the hardware accelerator processes polynomial multiplication in iterative segments rather than requiring all computational resources simultaneously. This dynamic segmentation allows the same hardware resources to be reused across multiple computational steps, achieving high computation speed with reduced chip area.
4Reliability
If polynomial multiplication is performed with large operands, then cryptographic security is maintained, but calculation time increases
Solution Approach 1:
The patent handles large polynomial operands by segmenting them into smaller fragments that can be multiplied more quickly. The iterative accumulation of partial products from these fragment multiplications maintains the security level of large operand multiplication while reducing the calculation time through manageable segment processing steps.
Data Source
AI summary
Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware solutions for cryptographic operations. The present invention provides an approach which simultaneously tackles all those points. It concerns a hardware accelerator for polynomial multiplication in extended Galois fields (GF), wherein the per se known Karatsuba method is iteratively applied in accordance with the invention. When using the invention the area requirement can be reduced for example from 6.2 mm2 to 2.1 mm2. The solution according to the invention also reduces the energy consumption in comparison with solutions in accordance with the state of the art by 30%.