Polycrystalline Silicon Deposition for Bonded SOI Wafer
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Solution Overview
Problem
Existing methods for manufacturing SOI wafers for high-frequency devices fail to prevent single crystallization of polycrystalline silicon layers during heat treatment, leading to reduced effectiveness as carrier trapping layers and increased manufacturing costs due to low deposition rates at lower temperatures.
Innovation Solution
A method involving the deposition of a polycrystalline silicon layer on a base wafer with a previously formed oxide film, followed by heat treatment in a hydrogen-containing atmosphere, prevents single crystallization and enhances deposition rate by using temperatures between 1050°C and 1200°C, ensuring the oxide film's integrity and removing impurities that could degrade high-frequency characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polycrystalline silicon layer is deposited at lower temperature to prevent single crystallization, then the carrier trapping effect is maintained, but the deposition rate decreases and manufacturing cost increases
Solution Approach 1:
The patent applies parameter changes by optimizing the deposition temperature to a specific range (900-1100°C) that balances two competing requirements: maintaining the polycrystalline structure for carrier trapping while achieving sufficient deposition rate. This temperature parameter optimization resolves the contradiction between reliability (carrier trapping effect) and productivity (deposition rate) by finding the optimal thermal window where both objectives are simultaneously satisfied.
2Ease of manufacture
If heat treatment is performed after depositing the polycrystalline silicon layer, then manufacturing process is completed, but single crystallization occurs reducing the carrier trapping effect
Solution Approach 1:
The patent applies preliminary action by performing specific preparatory steps before the final heat treatment that prevent single crystallization during subsequent processing. This includes controlling the deposition conditions and implementing protective measures prior to heat treatment, thereby enabling completion of the manufacturing process while preserving the polycrystalline structure and carrier trapping effect.
3Productivity
If deposition temperature is increased to improve deposition rate, then throughput increases, but single crystallization of the polycrystalline silicon layer occurs
Solution Approach 1:
The patent applies parameter changes by establishing a specific deposition temperature range (900-1100°C) that simultaneously achieves high deposition rate and maintains polycrystalline structure stability. This parameter optimization resolves the contradiction between productivity (throughput) and stability (polycrystalline structure) by identifying the optimal thermal window where rapid deposition occurs without triggering single crystallization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the effective prevention of single crystallization, improves throughput, and reduces manufacturing costs by maintaining the polycrystalline silicon layer's condition as a carrier trapping layer while ensuring high-frequency characteristics are preserved.
Implementation Method 1
a step of previously forming an oxide film having a thickness thicker than 10 nm and less than or equal to 30 nm on a surface of the base wafer on which the polycrystalline silicon layer is to be deposited
Implementation Method 2
after forming the oxide film and before depositing the polycrystalline silicon layer, a heat treatment is performed at 1050°C or more and 1200°C or less for 1 second or more and 60 seconds or less under a hydrogen-containing atmosphere
Implementation Method 3
the polycrystalline silicon layer is deposited at 1050°C or more and 1200°C or less
Data Source
Figure 1
Figure 2(a)~2(i)
AI summary
The present invention is a method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the polycrystalline silicon layer with the insulator film being interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 Ω·cm or more is used as the base wafer, the step of depositing the polycrystalline silicon layer includes a stage of previously forming an oxide film having a thickness of 10 nm or more and 30 nm or less on the surface of the base wafer on which the polycrystalline silicon layer is to be deposited, and the polycrystalline silicon layer is deposited at 1050°C or more and 1200°C or less. As a result, there can be provided a method for manufacturing a bonded SOI wafer that enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.