Polysilicon Sacrificial Gate Etching for Stable FinFET Profiles
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Solution Overview
Problem
In the semiconductor industry, the variation in the profile of polysilicon sacrificial gate electrodes during the etching process leads to inconsistent device performance and low yield due to uncontrolled wafer-to-wafer variations in metal gate FinFETs, affecting parameters like driving current, threshold voltage, and switching speed.
Innovation Solution
A method is introduced to control the profile of the sacrificial gate electrode by forming a coating material layer in the etching chamber, adjusting conditions such as pressure and gas flow ratios to stabilize the etching process, thereby ensuring consistent polysilicon pattern formation and subsequent metal gate profile design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching process is used for polysilicon sacrificial gate electrode, then manufacturing simplicity is maintained, but profile variation and device performance inconsistency occur
Solution Approach 1:
A coating material layer is formed on the inner wall of the etching chamber before the polysilicon etching process. This preliminary action creates a controlled etching environment that stabilizes the etch rate and reduces wafer-to-wafer variations in polysilicon profile, thereby improving manufacturing precision without significantly increasing process complexity
Solution Approach 2:
The etching process parameters are optimized by controlling the coating material layer formation conditions (pressure, gas flow ratios). By adjusting these parameters, the etching rate and profile consistency are improved, resolving the contradiction between manufacturing precision and process complexity
2Reliability
If etching process is performed without coating material layer, then process simplicity is maintained, but wafer-to-wafer variation increases
Solution Approach 1:
The coating material layer is deposited on the etching chamber wall before polysilicon etching. This preliminary step ensures consistent etching conditions across wafers, improving device performance consistency while the automated nature of the process minimizes the impact on manufacturing efficiency
3Manufacturing precision
If coating material layer is formed with optimized pressure and gas flow, then polysilicon profile control is improved, but process time increases
Solution Approach 1:
The pressure and gas flow ratios are optimized to achieve the desired polysilicon profile while minimizing process time. By finding the optimal parameter combination, the coating material layer formation and etching process are balanced to improve profile control without excessive time penalty
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance and yield by reducing wafer-to-wafer variations in the sacrificial gate electrode profiles, leading to more reliable and consistent electrical properties in metal gate FinFETs.
Implementation Method 1
a coating material layer is formed on an inner wall of an etching chamber
Implementation Method 2
the polysilicon layer is etched by plasma dry etching
Data Source
AI summary
A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.