Polysilicon Gate Planarization Using Polishing Stop Layers
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in achieving better planarity over memory cell and core logic device regions due to complex structures and different formation processes, leading to poor top surface topology that affects subsequent fabrication processes.
Innovation Solution
A semiconductor device and method involving gate structures with spacers, polysilicon layers, and polishing stop layers are used to improve planarity, including a conformal polysilicon layer and sacrificial layers with anisotropic etching processes to expose and remove material, resulting in a planarized top surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex memory cell and core logic device structures are fabricated together in a single integrated semiconductor device, then the device functionality and capability are improved, but the planarity and top surface topology deteriorate due to different fabrication processes
Solution Approach 1:
The patent divides the semiconductor device into distinct cell region and core region, each with their own gate structures and polishing stop layers. This segmentation allows independent optimization of each region's fabrication process while maintaining overall integration, resolving the planarity issue caused by combining different device types in a single device.
Solution Approach 2:
The patent introduces preliminary polishing stop layers (first and second polishing stop layers) before final planarization. These stop layers are deposited in advance to establish reference planes that guide subsequent polishing processes, ensuring that both cell and core regions achieve proper planarity despite their different fabrication requirements.
2Reliability
If different fabrication processes are used for memory cell and core logic device regions, then the device performance is improved, but the top surface topology and planarity worsen
Solution Approach 1:
The patent applies different structures and processes to different regions: the cell region has gate structures with spacers and first polishing stop layers, while the core region has preliminary material layers with second polishing stop layers. This local differentiation allows each region to be optimized for its specific function while the overall surface planarity is maintained through coordinated polishing processes.
Solution Approach 2:
The polishing stop layers act as intermediary elements between the different fabrication processes of the cell and core regions. These stop layers provide a common reference plane that mediates the planarization process, allowing the two regions with different fabrication histories to achieve compatible surface topologies for subsequent integrated processing.
3Manufacturing precision
If multiple polysilicon layers and polishing stop layers are added to achieve planarity, then the surface flatness is improved, but the device structure complexity increases
Solution Approach 1:
The polishing stop layers serve multiple functions: they act as etch stops during anisotropic etching, as reference planes for polishing processes, and as structural elements that define the final surface topology. This multi-functionality reduces the need for additional dedicated planarization layers, managing complexity while achieving surface flatness.
Solution Approach 2:
The patent combines the planarization function with the existing gate structure fabrication process. The first and second polishing stop layers are integrated into the gate structure formation process rather than being added as separate post-processing steps, merging structure formation with surface planarization to avoid excessive complexity.
4Manufacturing precision
If anisotropic etching and polishing processes are used to remove material and expose polysilicon layers, then the planarity is improved, but the fabrication process complexity increases
Solution Approach 1:
The patent employs periodic alternating actions of anisotropic etching and polishing processes. The anisotropic etching selectively removes material to expose polysilicon layers, followed by polishing to restore surface flatness. This periodic cycle of etching and polishing is repeated as needed to achieve the desired planarity while managing process complexity through systematic iteration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach achieves improved planarity over the semiconductor device regions, facilitating subsequent fabrication processes by ensuring a flat surface and reducing polishing load, thereby enhancing the overall fabrication efficiency.
Implementation Method 1
A preliminary polishing process is performed over the substrate to at least expose a portion of the polysilicon layer over the gate structures
Implementation Method 2
performing an anisotropic etching process from the exposed portion of the polysilicon layer until the sacrificial layer is exposed
Data Source
AI summary
A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.