Polysilicon Grain Size Reduction via Backside Dielectric Exposure
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Solution Overview
Problem
Conventional semiconductor manufacturing methods result in large grain size polysilicon, leading to implant dopant penetration into the silicon substrate, which deteriorates the electrical properties of the device and requires thermal processes that are not effectively managed.
Innovation Solution
A method where a dielectric layer is exposed as the outermost layer at the backside of the silicon substrate during polysilicon deposition, allowing silane or disilane to flow from the wafer edge to center, thereby reducing the grain size of polysilicon and preventing dopant penetration without thermal changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional thermal processes are used for polysilicon deposition, then the deposition process can be completed, but the grain size of polysilicon increases leading to implant penetration and deterioration of electrical properties
Solution Approach 1:
The patent changes the deposition parameters by using plasma-enhanced chemical vapor deposition (PECVD) instead of conventional thermal deposition, depositing polysilicon at lower temperatures (300-450°C) to suppress grain growth while maintaining deposition efficiency and electrical properties
Solution Approach 2:
The patent uses a composite approach by forming a polysilicon-nitride composite structure where a nitride layer is deposited on top of the polysilicon layer, creating a composite material system that prevents implant penetration and controls grain size simultaneously
2Ease of manufacture
If thermal processes are used to deposit polysilicon, then the polysilicon layer can be formed, but thermal budget increases causing unwanted thermal effects on the device
Solution Approach 1:
The patent replaces thermal deposition with plasma-enhanced chemical vapor deposition (PECVD), substituting a thermal process with a plasma-based process that achieves polysilicon deposition at lower temperatures, thereby reducing thermal budget while maintaining manufacturability
Solution Approach 2:
The patent uses an inert plasma environment (silane-based plasma) for polysilicon deposition, creating a controlled inert atmosphere that enables low-temperature deposition without oxidation or unwanted thermal reactions, preserving device integrity
3Device complexity
If polysilicon with large grain size is formed on the silicon substrate, then the deposition process is simpler, but implant dopant penetrates through the channel to the substrate causing device failure
Solution Approach 1:
The patent changes deposition parameters to produce fine-grained polysilicon with grain sizes controlled at 0.5-2 micrometers through PECVD processes, creating a denser polysilicon structure that acts as an effective barrier against implant dopant penetration while maintaining process feasibility
Solution Approach 2:
The patent creates a polysilicon-nitride composite structure where the nitride layer is deposited on the polysilicon, forming a composite barrier system that enhances resistance to implant penetration and provides dual functionality for device protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces polysilicon grain size, improves electrical properties by eliminating macro leakage and increasing yield, and maintains improved semiconductor device performance without thermal budge changes.
Implementation Method 1
depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.