Polysilicon Storage Electrode Planarization via Three-Step Etching
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Solution Overview
Problem
As design rules for semiconductor memory devices decrease, the formation of capacitors with sufficient capacitance in limited areas becomes challenging due to increased patterning issues caused by step differences and surface roughness, leading to complex processes and increased manufacturing costs.
Innovation Solution
A method for forming a storage electrode in semiconductor memory devices involves a sequence of etching processes using specific gases to create a planarized storage node contact, including a first etching process with chlorine gas, a second over-etching process with hexafluoroethane, and a third planarization process with a helium, oxygen, and argon gas mixture, which simplifies the process and improves surface topology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CMP process is used to separate storage node contacts, then contacts are separated, but dishing phenomenon and wave-shaped topology defects occur
Solution Approach 1:
The patent changes the etching parameters by using a three-step etching process with different gases (Cl2, C2F6, and He/O2/Ar mixture) instead of conventional CMP. This transforms the physical state and chemical properties of the polysilicon layer during processing, achieving planarization through controlled etching rather than mechanical polishing, thereby eliminating dishing and wave-shaped defects
Solution Approach 2:
The patent replaces the mechanical CMP (chemical mechanical polishing) system with a chemical etching system using plasma-based gas etching. This substitution eliminates the mechanical contact that causes dishing and surface deformation, achieving contact separation through chemical reactions controlled by the three-step gas etching process
2Reliability
If over etch is performed to compensate for defective topology, then contact separation is ensured, but process margin is significantly reduced
Solution Approach 1:
The patent performs preliminary planarization by depositing an additional polysilicon layer before the etching process. This preliminary action creates a uniform starting surface that compensates for any future etching variations, ensuring reliable contact separation while maintaining adequate process margins through the controlled three-step etching process
3Manufacturing precision
If additional planarization process is performed on mold insulating layer, then surface defects are corrected, but manufacturing time and cost increase
Solution Approach 1:
The patent performs preliminary planarization of the polysilicon layer itself through the three-step etching process before depositing the mold insulating layer. This preliminary action ensures that the mold insulating layer is deposited on a planar surface, eliminating the need for subsequent planarization processes and maintaining high manufacturing efficiency
Solution Approach 2:
The patent extracts the planarization function from the mold insulating layer processing stage and transfers it to the polysilicon layer processing stage. By achieving planarity during contact formation, the patent eliminates the need for additional planarization steps on the mold insulating layer, reducing manufacturing time and cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a storage node contact with a good surface topology, reducing the need for subsequent planarization of the mold insulating layer, thereby simplifying processes, improving process margins, and reducing manufacturing costs.
Implementation Method 1
a first etching process for etching the polysilicon layer to a predetermined thickness
Implementation Method 2
a second etching process for over-etching the polysilicon layer
Implementation Method 3
a third etching process for planarizing a surface of the polysilicon layer
Implementation Method 4
a third etching process for planarizing a surface of the polysilicon layer
Data Source
AI summary
In order to form a storage electrode of a semiconductor memory device, an interlayer dielectric layer is formed on a semiconductor substrate having a bit line thereon. A contact hole exposing the semiconductor substrate is formed by patterning the interlayer dielectric layer. A polysilicon layer is etched to a predetermined thickness using polysilicon etching gas after the polysilicon layer is deposited. An over-etch process is performed relative to the polysilicon layer, and then a storage node contact having a planarized surface is formed in the contact hole by performing an etching process for planarizing the surface of the polysilicon layer. A mold insulating layer is formed on the resultant structure, in which the mold insulating layer exposes an area where the storage node contact is formed. A storage electrode coupled to the storage node contact is formed.