Polycrystalline Silicon Susceptor Layer for Etch Uniformity
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Solution Overview
Problem
Conventional methods for etching semiconductor structures face challenges in achieving uniformity due to edge boundary effects, particularly in advanced CMOS device fabrication, where localized disruptions in heat transfer, momentum transport, and mass transport lead to edge roll-off and non-uniform thickness.
Innovation Solution
A method involving a processing reactor with a susceptor coated with a polycrystalline silicon surface layer, where the layer is deposited at a temperature below 1150°C and modified with etchants to increase its surface area, reducing edge loading effects and improving thickness uniformity during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used in a single-wafer thermal process chamber, then the etching process is simple and fast, but edge boundary effects occur causing non-uniform thickness and edge roll-off
Solution Approach 1:
A polycrystalline silicon surface layer is deposited on the susceptor to act as an intermediary between the semiconductor structure and the susceptor. This intermediate layer modifies the thermal and mass transport characteristics at the boundary region, reducing edge boundary effects and improving thickness uniformity during etching without requiring complex process changes
Solution Approach 2:
The surface properties of the susceptor are changed by depositing a polycrystalline silicon layer and modifying it with etchants to increase surface area. This parameter change in the susceptor surface characteristics alters the heat transfer and mass transport conditions, mitigating edge roll-off and improving etching uniformity
2Manufacturing precision
If the gap between the wafer edge and susceptor is increased to reduce edge effects, then edge boundary effects are reduced, but manufacturing tolerances and thermal expansion become limiting factors
Solution Approach 1:
The polycrystalline silicon surface layer serves as a mediator that reduces edge boundary effects without requiring increased gap dimensions. By modifying the susceptor surface properties, the technique achieves improved edge uniformity while maintaining standard manufacturing tolerances and gap dimensions
3Manufacturing precision
If the pocket height is increased to extend the affected region toward the inner region, then the affected region is extended, but this does not improve azimuthal thickness uniformity determined by centering
Solution Approach 1:
The polycrystalline silicon surface layer acts as an intermediary that improves azimuthal thickness uniformity by modifying the susceptor surface properties. This approach addresses the centering issue without requiring changes to pocket height or other geometric parameters
Solution Approach 2:
The etchant treatment creates local quality changes in the polycrystalline silicon surface layer, specifically increasing surface area at critical regions. This localized modification improves azimuthal thickness uniformity without affecting the overall pocket geometry or centering requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased surface area of the polycrystalline silicon layer enhances etch rate and uniformity, reducing edge roll-off and improving azimuthal thickness uniformity across the semiconductor structure.
Implementation Method 1
A polycrystalline silicon surface layer is deposited on the susceptor at a temperature of less than 1150° C.
Implementation Method 2
A grooving etchant is introduced into the processing reactor without a semiconductor structure being disposed on the susceptor. The grooving etchant contacts the polycrystalline silicon surface layer to produce a surface-modified polycrystalline silicon surface layer.
Implementation Method 3
The semiconductor structure is contacted with a second etchant to etch the semiconductor structure.
Data Source
AI summary
Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.