Polysilicon Thin Film Transistor Bottom Gate Structure
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Solution Overview
Problem
The existing polysilicon thin film transistors in flat panel displays face challenges such as high production costs and difficulty in forming top gate structures due to issues with crystallization processes, which affect the field effect mobility and uniformity of the transistors.
Innovation Solution
A thin film transistor array panel with a bottom gate structure using polysilicon semiconductors, where the control electrode is made of refractory conductors and the gate line of low resistivity materials, along with a manufacturing method that includes forming a polysilicon semiconductor layer by crystallizing amorphous silicon, simplifying the production process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heat treatment is used for crystallization of amorphous silicon, then polysilicon thin film can be formed, but the gate conductor is affected by heat and production cost increases
Solution Approach 1:
A buffer layer is introduced between the gate conductor and the amorphous silicon layer. This buffer layer serves as a thermal barrier during crystallization, protecting the gate conductor from heat damage while allowing the amorphous silicon to be converted to polysilicon through laser irradiation or heat treatment
Solution Approach 2:
The patent replaces conventional heat treatment with laser beam irradiation for crystallization. The laser provides localized, controlled energy that converts amorphous silicon to polysilicon without requiring high-temperature processing that would affect the gate conductor
2Manufacturing precision
If laser beam irradiation is used for crystallization, then uniform crystallization is difficult to obtain due to reflection by gate conductor, but heat treatment affects gate conductor
Solution Approach 1:
The buffer layer acts as an intermediary that prevents laser reflection from the gate conductor, enabling uniform crystallization of the amorphous silicon layer without compromising the gate conductor
Solution Approach 2:
The buffer layer is designed to have optical properties that match the surrounding materials, reducing reflection and enabling uniform laser energy distribution across the amorphous silicon layer
3Reliability
If top gate structure is used for polysilicon TFT, then field effect mobility improves, but difficulty in forming structure and high production cost increase
Solution Approach 1:
Instead of using a top gate structure where the gate is formed after the semiconductor layer, the patent employs a bottom gate structure where the gate conductor is formed first, followed by the buffer layer and then the polysilicon semiconductor layer. This inversion simplifies the manufacturing process while maintaining high field effect mobility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high electric field effect mobility and reduces signal delay or distortion in the transistors, while simplifying the manufacturing method and lowering production costs, making it suitable for high-frequency operations in displays like OLEDs.
Implementation Method 1
The polysilicon thin film is formed by depositing an amorphous silicon thin film and crystallizing the deposited amorphous silicon thin film. Here, the crystallization is performed by heat treatment at a high temperature or by laser beam irradiation, for example.
Implementation Method 2
the crystallization is performed by heat treatment at a high temperature or by laser beam irradiation
Data Source
AI summary
The present invention relates to an OLED display and a manufacturing method thereof, including a substrate, a control electrode formed on the substrate, a polysilicon semiconductor formed on the control electrode, a data line including an input electrode at least partially overlapping the polysilicon semiconductor and an output electrode facing the input electrode, an insulating layer covering the data line and the output electrode and having a contact hole, a gate line connected to the control electrode through the contact hole, and a pixel electrode connected to the output electrode.