Polysilicon TFT Gettering Gate Metal Layer
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Solution Overview
Problem
The existing methods for crystallizing amorphous silicon into polysilicon for thin film transistors, such as solid phase crystallization and excimer laser crystallization, face issues like long process times, high temperatures, and increased manufacturing costs due to the need for additional gettering processes to remove metal catalysts, which can lead to leakage currents and interface deterioration.
Innovation Solution
A manufacturing method for thin film transistors that involves forming a polysilicon layer using a metal catalyst, followed by a gettering heat treatment to move residual metal catalysts to a gate metal layer, eliminating the need for an additional gettering metal layer and simplifying the process, thereby reducing costs and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a metal catalyst is used to crystallize amorphous silicon into polysilicon, then crystallization can be achieved at lower temperature and shorter time, but residual metal catalyst remains in the channel area causing increased leakage current
Solution Approach 1:
The patent extracts the harmful metal catalyst from the channel area by introducing a gettering metal layer that selectively absorbs and traps the residual catalyst atoms, removing them from the active transistor region to reduce leakage current
Solution Approach 2:
The gettering metal layer acts as an intermediary between the polysilicon layer and the channel area, serving as a trap site that captures metal catalyst atoms and prevents them from remaining in the channel where they would cause leakage
2Reliability
If an additional gettering metal layer is formed and gettering process is performed, then leakage current is reduced, but manufacturing cost increases and process becomes more complex
Solution Approach 1:
The patent combines the gettering metal layer formation with the existing gate electrode formation process by using the same metal layer and patterning steps, thereby integrating two functions into one process sequence and reducing overall manufacturing complexity
Solution Approach 2:
The gate electrode metal layer is given dual functionality: it serves as both the gate electrode for transistor operation and as the gettering metal layer for capturing residual catalyst, eliminating the need for a separate dedicated gettering layer
3Productivity
If excimer laser crystallization is used, then crystallization is achieved quickly, but protrusions are formed at crystallized surface deteriorating interface characteristic between semiconductor layer and gate insulating layer
Solution Approach 1:
The patent uses a low-cost, short-duration thermal annealing process instead of expensive excimer laser equipment, achieving sufficient crystallization without the harmful protrusion effects caused by intense localized laser heating
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces leakage currents and simplifies the manufacturing process, minimizing production costs and improving the interface characteristics between semiconductor and gate insulating layers.
Implementation Method 1
a method for crystallizing an amorphous silicon layer using a metal catalyst has been actively studied because the method is more advantageous in crystallization at a lower temperature within a short period of time
Implementation Method 2
moving residual metal catalysts in the semiconductor layer to the gate metal layer that contacts the semiconductor layer by performing gettering heat treatment on the semiconductor layer
Data Source
AI summary
A thin film transistor may include a substrate, a buffer layer on the substrate, a semiconductor layer formed on the buffer layer, a gate insulating pattern on the semiconductor layer, a gate electrode on the gate insulating pattern, an interlayer insulating layer covering the gate electrode and the gate insulating pattern, the interlayer insulating layer having a contact hole and an opening extending therethrough, the contact hole exposing a source area and a drain area of the semiconductor layer, and the opening exposing a channel area of the semiconductor layer, and a source electrode and a drain electrode formed on the interlayer insulating layer, the source electrode being connected with the source area and the drain electrode being connected with the drain area of the semiconductor layer.