Pooling and Unpooling Hardware Acceleration via Fixed-Function Circuitry
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Solution Overview
Problem
Neural network accelerators (NNAs) face inefficiencies in performing argmax/argmin functions, pooling, unpooling, and binary argmax/argmin operations due to limited specialized hardware and high overhead in data transfer when using general-purpose processors, leading to performance degradation and resource underutilization.
Innovation Solution
Repurpose existing fixed-function circuitry in NNAs to perform these operations using elementary neural network operations such as element-wise subtraction, multiplication, maximum, minimum, pooling, and deconvolution operations, eliminating the need for dedicated hardware and reducing data transfer overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose processors are used to perform argmax/argmin and pooling operations, then flexibility and adaptability are improved, but processing speed and resource utilization deteriorate due to high data transfer overhead
Solution Approach 1:
The patent merges the pooling operation with the argmax/argmin operation into a single integrated hardware unit. This combination eliminates the need for separate processing steps and data transfers between general-purpose processors and specialized units, thereby maintaining flexibility while significantly improving processing speed and resource utilization.
Solution Approach 2:
The patent designs a universal pooling unit that can perform multiple functions including max pooling, min pooling, argmax, and argmin operations. This multi-functional unit replaces the need for separate dedicated hardware for each operation, providing both flexibility and high-speed processing within a single integrated component.
2Productivity
If dedicated hardware is added to NNAs for argmax/argmin and pooling operations, then processing speed is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple functions (pooling, argmax, argmin) into a single integrated hardware unit, reducing the overall number of separate components needed in the NNA. This merger maintains high processing speed while reducing device complexity and manufacturing cost compared to having separate dedicated hardware for each operation.
Solution Approach 2:
The universal pooling unit is designed to handle multiple operations (max pooling, min pooling, argmax, argmin) within a single hardware structure. This multi-functionality reduces the need for additional specialized hardware, thereby improving processing speed without proportionally increasing device complexity.
3Measurement precision
If separate hardware units are implemented for pooling and argmax/argmin operations, then functional precision is improved, but resource utilization and efficiency deteriorate
Solution Approach 1:
The patent merges pooling and argmax/argmin operations into a single hardware unit that processes data through both functions in sequence without intermediate data transfers. This integration maintains the functional precision of separate units while eliminating the resource overhead of separate hardware implementations, thereby improving resource utilization and efficiency.
Data Source
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AI summary
A mechanism for processing, on a hardware accelerator comprising fixed-function circuitry, data according to a neural network process that includes a pooling, unpooling or backward pooling and/or binary argmax/argmin function. The function is mapped to a set of elementary neural network operations available to the fixed-function circuitry. The neural network process is then executed using the fixed-function circuitry. The data processed using the neural network process comprises image and/or audio data.