Package-on-Package Assembly Warpage Control via Dummy Chip and TSV
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Solution Overview
Problem
Current Package-on-Package (PoP) assemblies face challenges with tight pitch stacking, large package form factor, and poor warpage control due to thick molding compounds, which hinder the assembly of dense microelectronic components and lead to wafer warpage issues.
Innovation Solution
The proposed PoP assembly includes a bottom die package with an interposer, active and TSV chips, and a molding compound, where the top die package is mounted using bumps on the TSV chip, and optionally uses dummy chips to reduce warpage by minimizing the molding compound usage and employing a redistribution layer and dielectric layers for precise chip mounting and connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thick layer of molding compound is used to cover the wafer and dies, then the packaging is more robust and provides better protection, but warpage increases due to CTE mismatch and increased thickness
Solution Approach 1:
The patent divides the packaging structure into multiple functional layers: a thin molding compound layer for basic protection, a planarization layer for surface flatness, and a redistribution layer for electrical connections. This segmentation allows each layer to perform its specific function without contributing excessively to warpage, solving the contradiction between protection and stability.
Solution Approach 2:
The patent changes the thickness parameter of the molding compound layer from traditionally thick to thin (e.g., 10-50 micrometers), and introduces additional layers with controlled thicknesses. This parameter optimization reduces the overall warpage while maintaining adequate protection through the combined structure of multiple layers.
2Ease of manufacture
If peripheral solder balls are used to interconnect top and bottom packages, then the assembly process is simplified, but tight pitch stacking cannot be achieved
Solution Approach 1:
The patent transitions from 2D peripheral solder ball connections to 3D vertical stacking with TSVs (Through-Silicon Vias) that penetrate through the substrate. This dimensional change enables tight pitch stacking by utilizing the vertical dimension for interconnections, while the redistribution layer provides the necessary routing flexibility.
Solution Approach 2:
The patent introduces an interposer substrate with redistribution layers as an intermediary between the active chip and the packaging substrate. This intermediary structure enables fine-pitch RDL processes and facilitates precise alignment and connection, solving the pitch stacking precision problem while maintaining manufacturing feasibility.
3Ease of operation
If the package form factor is enlarged to accommodate all components, then component placement is easier, but the overall package size increases
Solution Approach 1:
The patent implements a nested structure where the active chip is mounted on the interposer substrate, which is in turn mounted on the packaging substrate. The TSVs provide vertical interconnections through the nested layers, enabling compact 3D stacking that reduces the horizontal footprint while maintaining ease of component placement through standardized mounting processes.
Solution Approach 2:
The patent moves from horizontal expansion to vertical stacking by utilizing TSVs that extend through the substrate thickness. This allows components to be arranged in multiple layers vertically, reducing the package form factor area while maintaining component placement feasibility through controlled placement sequences.
4Productivity
If wafer level packaging is used for fine-pitch RDL process, then integration density is improved, but warpage prevents successful die-to-wafer assembly
Solution Approach 1:
The patent segments the packaging into a thin molding compound layer (10-50 micrometers), a separate planarization layer, and a redistribution layer. This segmentation reduces the thickness of each individual layer, minimizing CTE mismatch effects and warpage while maintaining the integration density benefits of wafer level packaging for fine-pitch RDL processes.
Solution Approach 2:
The patent employs a composite structure with multiple materials having different properties: a thin molding compound for protection, a planarization layer (possibly with different CTE) for surface flatness, and a redistribution layer for electrical connections. This composite approach allows optimization of each material's properties to reduce overall warpage while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for reduced warpage and improved assembly precision, enabling successful die-to-wafer stacking and fine-pitch RDL processes, particularly in large-sized wafers, by optimizing the use of molding compound and leveraging TSVs and dummy chips for enhanced warpage control.
Implementation Method 1
The top die package is interconnected to the bottom package through peripheral solder balls
Implementation Method 2
The thick layer of the molding compound results in increased warping of the packaging due to coefficient of thermal expansion (CTE) mismatch
Implementation Method 3
at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps
Data Source
AI summary
A package-on-package (PoP) assembly includes a bottom die package and a top die package. The bottom die package includes an interposer having a first side and a second side, an active chip mounted on the first side within a chip mounting area through first bumps, and a dummy chip mounted on the first side within a peripheral area. The dummy chip is directly mounted on a passivation layer of the interposer. A dielectric layer covers the active chip and the dummy chip. At least one TSV connecter penetrates through the dielectric layer and the dummy chip. A molding compound is disposed on the first side. The molding compound covers the active chip and the TSV chip. Solder bumps are mounted on the second side.