Package-on-Package Interconnect Structure for 3D Integration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces limitations in increasing integration density due to physical constraints in two-dimensional integrated circuits, leading to increased circuit RC delay and power consumption, which are addressed by transitioning to three-dimensional integrated circuits (3DICs) through package-on-package (PoP) structures using through-silicon vias (TSVs) for enhanced connectivity.

Innovation Solution

A method for manufacturing a PoP structure involves forming a protective layer over an integrated circuit die, depositing a seed layer, creating patterned through vias, and using redistribution layers to connect dies stacked within a molding compound, with the protective layer extending over the dies to reduce warpage and improve bonding, while also allowing for electrical connections through contact pad openings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If more devices are integrated into one chip to increase integration density, then the number of components increases, but circuit RC delay and power consumption increase significantly

Engineering Contradiction:
Improveintegration densityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent transitions from two-dimensional planar integration to three-dimensional stacked integration using package-on-package technology. Multiple dies are stacked vertically and connected through through-silicon vias (TSVs), enabling higher integration density without proportionally increasing interconnection length and power consumption.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The system is divided into multiple separate packages (first package, second package) that are stacked and interconnected. Each package contains specific functional blocks, and TSVs provide vertical interconnections between packages, segmenting the overall system into manageable modular units.

Inventive Principle:
Principle #1Segmentation

2Reliability

If through-silicon vias are used to connect stacked dies, then connectivity between packages is enhanced, but manufacturing complexity increases

Engineering Contradiction:
ImproveconnectivityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

TSVs are formed and conductive plugs are deposited into the vias before the final packaging and stacking process. This preliminary formation of interconnection structures simplifies subsequent assembly steps and ensures reliable electrical connections are established prior to final device operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A protective layer is introduced as an intermediary element between the semiconductor dies and the external environment. This protective layer extends over the dies and provides mechanical support and protection during bonding processes, facilitating reliable package-on-package assembly.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If a protective layer is extended over the dies, then warpage is controlled and bonding is improved, but the area occupied by the structure increases

Engineering Contradiction:
Improvewarpage controlVSAvoidstructure area
Core Design Contradiction:
Stability of the object's compositionVSArea of stationary object

Solution Approach 1:

A thin protective layer is deposited over the semiconductor dies to provide mechanical support and control warpage during the packaging process. This thin film approach provides the necessary structural stability without significantly increasing the overall device area.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables higher density electronics by reducing die shift and solder ball cracking, controlling warpage, and enhancing electrical connections, thereby improving the performance and efficiency of 3DICs by minimizing RC delay and power consumption.

Implementation Method 1

depositing a seed layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS11037861B2Interconnect structure for package-on-package devices
Publication Date: 2021.06.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11037861B2 patent drawing
  • US11037861B2 patent drawing
  • US11037861B2 patent drawing

AI summary

An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.