Porous Capacitor Electrode Structure for High Capacitance

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Solution Overview

Problem

Conventional capacitors face challenges in achieving a balance between high capacitance and mechanical strength, as well as in manufacturing processes where porosity and parasitic resistance are concerned, due to the design of conductive substrates and dielectric layers.

Innovation Solution

A capacitor design featuring a conductive substrate with recesses and holes of varying porosity, where the first main surface has a higher porosity than the second main surface, and a conductive layer and dielectric layer are applied to cover and fill these structures, enhancing capacitance while minimizing parasitic resistance and mechanical damage during manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the conductive substrate has high porosity to increase capacitance, then the electric capacitance is improved, but the mechanical strength deteriorates

Engineering Contradiction:
Improveelectric capacitanceVSAvoidmechanical strength
Core Design Contradiction:
Quantity of substanceVSStrength

Solution Approach 1:

The conductive substrate has different porosity in different regions: a first region with higher porosity (30-80%) and a second region with lower porosity (0-20%). This local differentiation allows the high porosity region to provide high capacitance while the low porosity region maintains mechanical strength, resolving the contradiction between capacitance and mechanical strength.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the conductive substrate has high porosity to increase capacitance, then the electric capacitance is improved, but the parasitic resistance increases

Engineering Contradiction:
Improveelectric capacitanceVSAvoidparasitic resistance
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The substrate structure with localized high porosity regions separated by low porosity regions reduces parasitic resistance by providing conductive pathways through the less porous regions while maintaining high capacitance in the porous regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention transitions from a uniform porosity structure to a spatially differentiated porosity structure, creating a three-dimensional arrangement where high porosity regions for capacitance are interconnected through lower porosity regions that provide conductive pathways, thereby reducing parasitic resistance while maintaining high capacitance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If the conductive substrate has high porosity to increase capacitance, then the electric capacitance is improved, but the risk of damage during manufacturing increases

Engineering Contradiction:
Improveelectric capacitanceVSAvoidrisk of damage during manufacturing
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

By creating regions of different porosity, the substrate has areas of high porosity for capacitance and areas of low porosity for structural integrity during manufacturing. The low porosity regions provide mechanical strength that reduces the risk of damage during handling and processing, while the high porosity regions provide the desired capacitance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11862667B2Capacitor
Publication Date: 2024.01.02 KK TOSHIBA
  • US11862667B2 patent drawing
  • US11862667B2 patent drawing
  • US11862667B2 patent drawing

AI summary

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.