Porous Silicon Nitride Inner Spacers for GAA Capacitance Control
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Solution Overview
Problem
Conventional gate-all-around (GAA) transistors face challenges in forming inner spacers that do not damage the epitaxial stack, provide etch selectivity, and maintain low parasitic capacitance, especially when using silicon oxide as the dielectric material.
Innovation Solution
Formation of inner spacers using a porous silicon nitride material deposited via ALD with organosilane precursors, treated to enhance crosslinking and porosity, and selectively etched to maintain device integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If silicon oxide is used as dielectric material for inner spacers, then low parasitic capacitance is achieved, but the epitaxial stack is oxidized and damaged
Solution Approach 1:
The patent employs porous silicon nitride material for inner spacer formation. The porous structure reduces the dielectric constant (k-value) of the material, thereby lowering parasitic capacitance between gate and source/drain regions. simultaneously, the porous structure allows controlled etching and prevents oxidation damage to the epitaxial stack during fabrication processes.
Solution Approach 2:
The patent changes the material parameter from conventional silicon oxide to silicon nitride with controlled porosity. By adjusting the porosity level, the dielectric constant is reduced to achieve low capacitance while maintaining compatibility with subsequent fabrication steps that would otherwise damage the epitaxial stack through oxidation.
2Ease of manufacture
If conventional inner spacer formation methods are used, then manufacturing simplicity is maintained, but etch selectivity is insufficient and device damage occurs
Solution Approach 1:
The porous structure of the silicon nitride inner spacer provides enhanced etch selectivity. The porous morphology allows differential etching rates between the inner spacer material and surrounding structures, enabling precise pattern transfer and selective removal where needed without damaging adjacent epitaxial components.
Solution Approach 2:
The inner spacer is formed as a composite structure combining silicon nitride base material with controlled porosity. This composite approach provides both the mechanical stability needed for manufacturing and the etch selectivity required for precise fabrication, resolving the contradiction between ease of manufacture and manufacturing precision.
3Strength
If dense silicon nitride is used for inner spacers, then structural strength is improved, but parasitic capacitance increases
Solution Approach 1:
The patent utilizes porous silicon nitride where the porosity is carefully controlled to balance mechanical strength and dielectric properties. The porous structure reduces density and dielectric constant (lowering capacitance) while maintaining sufficient structural integrity through the silicon nitride framework and optimized pore distribution.
Solution Approach 2:
The patent optimizes the porosity parameter of the silicon nitride material to achieve the desired balance. By controlling porosity within specific ranges, the material maintains adequate mechanical strength for device fabrication while achieving reduced dielectric constant for low parasitic capacitance performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enlarges the process window for inner spacer formation, reduces parasitic capacitance, and improves device performance by using a low-k dielectric material that does not oxidize the epitaxial stack.
Implementation Method 1
Formation of inner spacers using a porous silicon nitride material deposited via ALD with organosilane precursors
Implementation Method 2
treated to enhance crosslinking and porosity
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.